EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 10

• Manufacturer Part Number: EP20K100EFC324-2
• Description: IC APEX 20KE FPGA 100K 324-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100EFC324-2

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 246
• Number Of Gates: 263000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 246
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APEX 20K Programmable Logic Device Family Data Sheet
Figure 2. MegaLAB Structure
10
LAB or IOEs
To Adjacent
Interconnect
Local
APEX 20K devices provide two dedicated clock pins and four dedicated
input pins that drive register control inputs. These signals ensure efficient
distribution of high-speed, low-skew control signals. These signals use
dedicated routing channels to provide short delays and low skews. Four
of the dedicated inputs drive four global signals. These four global signals
can also be driven by internal logic, providing an ideal solution for a clock
divider or internally generated asynchronous clear signals with high
fan-out. The dedicated clock pins featured on the APEX 20K devices can
also feed logic. The devices also feature ClockLock and ClockBoost clock
management circuitry. APEX 20KE devices provide two additional
dedicated clock pins, for a total of four dedicated clock pins.
MegaLAB Structure
APEX 20K devices are constructed from a series of MegaLAB
structures. Each MegaLAB structure contains a group of logic array blocks
(LABs), one ESB, and a MegaLAB interconnect, which routes signals
within the MegaLAB structure. The EP20K30E device has 10 LABs,
EP20K60E through EP20K600E devices have 16 LABs, and the
EP20K1000E and EP20K1500E devices have 24 LABs. Signals are routed
between MegaLAB structures and I/O pins via the FastTrack
Interconnect. In addition, edge LABs can be driven by I/O pins through
the local interconnect.
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
MegaLAB Interconnect
Figure 2
LE7
LE8
LE1
LE2
LE3
LE4
LE5
LE6
LE9
LE10
shows the MegaLAB structure.
LABs
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
Altera Corporation
TM
ESB