EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 181
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
Figure 6–4. Number of I/Os in Each Bank in EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA Package
Figure 6–5. Number of I/Os in Each Bank in EP4SE360, EP4SE530, and EP4SE820 Devices in the 1152-Pin FineLine BGA
Package
February 2011 Altera Corporation
1
Figure 6–4
information for different sets of available devices. They show the top view of the
silicon die that corresponds to a reverse view for flip chip packages. They are
graphical representations only.
For
dedicated clock pins, and dual purpose configuration pins. Transceiver pins and
dedicated configuration pins are not included in the pin count.
Number
of I/Os
48
42
42
48
Figure 6–4
Name
Bank 1A
Bank 1C
Bank 2C
Bank
Bank 2A
Number
of I/Os
through
32
26
26
32
Name
through
Bank 1A
Bank
Bank 1C
Bank 2C
Bank 2A
Figure 6–16
Figure
EP4SE360
EP4SE530
EP4SE820
EP4SE230
EP4SE360
6–16, the pin count includes all general purpose I/Os,
show the number of I/O pins and packaging
Bank 6A
Bank 6C
Bank 5C
Bank 5A
Name
Bank
Number
of I/Os
Bank 6A
Bank 6C
Bank 5C
Bank 5A
32
32
26
26
Name
Bank
Number
of I/Os
Stratix IV Device Handbook Volume 1
48
42
48
42
6–9
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