EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 998
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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1–40
Table 1–12. MegaWizard Plug-In Manager Options (Word Aligner Screen) (Part 2 of 4)
Stratix IV Device Handbook Volume 3
Number of continuous valid
code groups received to
reduce the error count by 1.
Number of erroneous code
groups (error count) received
to lose synchronization.
Number of valid code groups
received to achieve
synchronization.
What is the word alignment
pattern length?
What is the word alignment
pattern?
ALTGX Setting
Use this option in Automatic Synchronization State
Machine mode to indicate the number of continuous
valid code groups that it must receive between
erroneous code groups to reduce the error count by
one. The rx_syncstatus stays high as long as the
error count is less than the programmed error count.
Use this option in Automatic Synchronization State
Machine mode to indicate the number of erroneous
code groups (error count) that it must receive to lose
synchronization. The loss-of-synch is indicated by the
rx_syncstatus signal going low.
Use this option in Automatic Synchronization State
Machine mode to indicate the number of word
alignment patterns that it must receive without
intermediate erroneous code groups to achieve
synchronization. The rx_syncstatus signal is driven
high to indicate that synchronization has been
achieved.
This option sets the word alignment pattern length.
The available choices depend on the following
conditions:
■
■
■
Enter the word alignment pattern in MSB to LSB order
with MSB at the left most bit position. The length of
the alignment pattern is based on the What is the
word alignment pattern length? option. The word
aligner restores the word boundary by looking for the
pattern that you enter here. For example, if you want to
set the word alignment pattern to /K28.5/:
■
■
Whether the data is 8B/10B encoded or not
Which mode is used in Single-width mode:
■
■
Which mode is used in Double-width mode:
■
■
You must enter the word alignment pattern
length: 10.
You must enter the word alignment pattern:
0101111100 (17C).
for 8-bit PCS-PMA Interface (8B/10B encoder
disabled), only 16 bits are allowed.
for 10-bit PCS-PMA, 7 and 10 bits are allowed.
for 16-bit PCS-PMA Interface (8B/10B encoder
disabled), 8, 16, and 32 bits are allowed.
for 20-bit PCS-PMA Interface, 7, 10, and 20 bits
are allowed.
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“Automatic Synchronization State
Machine Mode Word Aligner with
10-bit PMA-PCS Interface Mode”
section in the
Architecture in Stratix IV Devices
chapter.
“Automatic Synchronization State
Machine Mode Word Aligner with
10-bit PMA-PCS Interface Mode”
section in the
Architecture in Stratix IV Devices
chapter.
“Automatic Synchronization State
Machine Mode Word Aligner with
10-bit PMA-PCS Interface Mode”
section in the
Architecture in Stratix IV Devices
chapter.
“Word Aligner in Single-Width
Mode” and “Word Aligner in
Double-Width Mode” sections in
the
Stratix IV Devices
“Word Aligner in Single-Width
Mode” and “Word Aligner in
Double-Width Mode” sections in
the
Stratix IV Devices
Transceiver Architecture in
Transceiver Architecture in
February 2011 Altera Corporation
Reference
Transceiver
Transceiver
Transceiver
chapter.
chapter.
Protocol Settings
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