EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 575
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–47. Datapaths in PCIe Mode
Table 1–48. Supported Features in PCIe Mode (Part 1 of 2)
February 2011 Altera Corporation
PCIe interface
Transmitter phase compensation FIFO
Optional byte serializer (enabled for 16-bit and disabled for
8-bit FPGA fabric-transceiver interface
8B/10B encoder
10:1 serializer
Transmitter buffer with receiver detect circuitry
Receiver buffer with signal detect circuitry
1:10 deserializer
Word aligner that implements PCIe-compliant synchronization
state machine
Optional rate match FIFO (clock rate compensation) that can
tolerate up to 600 PPM frequency difference
8B/10B decoder
Optional byte deserializer (enabled for 16-bit and disabled for
8-bit FPGA fabric-transceiver interface)
Receiver phase compensation FIFO
×1, ×4, ×8 link configurations
PCIe-compliant synchronization state machine
±300 PPM (total 600 PPM) clock rate compensation
8-bit FPGA fabric-transceiver interface
16-bit FPGA fabric-transceiver interface
Transmitter buffer electrical idle
Receiver Detection
8B/10B encoder disparity control when transmitting compliance
pattern
Power state management
f
Transceiver datapath clocking varies between non-bonded (×1) and bonded (×4 and
×8) configurations in PCIe mode.
For more information about transceiver datapath clocking in different PCIe
configurations, refer to the
Table 1–47
Table 1–48
5 Gbps data rate configurations.
For more information, refer to
Feature
lists the transmitter and receiver datapaths in PCIe mode.
lists the features supported in PCIe functional mode for 2.5 Gbps and
Transceiver Clocking in Stratix IV Devices
“Rate Match FIFO in PCIe Mode” on page
Transmitter Datapath
v
v
v
v
v
v
—
—
—
—
—
—
—
2.5 Gbps
Stratix IV Device Handbook Volume 2: Transceivers
(Gen1)
v
v
v
v
v
v
v
v
v
Receiver Datapath
chapter.
5 Gbps
v
v
v
v
v
v
v
v
—
—
—
—
—
(Gen2)
1–78.
v
v
v
v
v
v
v
v
—
1–131
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