EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 699
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
1
Bonded Channel Configurations
In PCS and PMA bonded channel configurations, the PCS and PMA blocks of all
bonded channels are clocked by the same low-speed parallel clock and high-speed
serial clock from the CMU0 clock divider or the ATX PLL block. The phase
compensation FIFOs of all bonded channels also share common read and write
pointers and enable signals generated in the CCU.
Stratix IV devices support ×4 PCS and PMA channel bonding that allows bonding of
four channels within the same transceiver block. Stratix IV devices also support ×8
channel bonding that allows bonding of eight PCS and PMA channels across two
transceiver blocks on the same side of the device.
The following functional modes support ×4 PCS and PMA bonded transmitter
channel configuration:
■
■
■
Use the CMU channels to generate the transceiver clocks for all ×4 bonded functional
modes listed above. Additionally, you may use the ATX PLLs to generate the
transceiver clocks for PCIe ×4 Gen 2 and Basic ×4 functional mode.
You must assign tx_dataout[0] of the ×4 bonded link (XAUI or PCIe ×4) to physical
channel 0 of the transceiver block, tx_dataout[1] to physical channel 1 of the
transceiver block, tx_dataout[2] to physical channel 2 of the transceiver block, and
tx_dataout[3] to physical channel 3 of the transceiver block. Otherwise, the
Quartus II compilation errors out.
PCIe ×4—Gen1 and Gen2
XAUI
Basic ×4
×4 PCS and PMA Bonded Channel Configuration
Stratix IV Device Handbook Volume 2: Transceivers
2–27
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