EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 639
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Auxiliary Transmit (ATX) PLL Block
Figure 1–159. PCIe Reverse Parallel Loopback Mode Datapath (Grayed-Out Blocks are Not Active in this Mode)
Auxiliary Transmit (ATX) PLL Block
February 2011 Altera Corporation
Fabric
FPGA
6G ATX PLL Block
f
f
In
parallel loopback mode is enabled.
Stratix IV GX and GT transceivers contain the ATX PLL block that you can use to
generate high-speed clocks for the transmitter channels on the same side of the
device. Each:
■
■
For data rates supported by these ATX PLLs, refer to the
Devices
Stratix IV GX can have either two (one on each side of the device) or four (two on each
side of the device) 6G ATX PLLs, depending on the specific devices.
For data rates supported by 6G ATX PLLs, refer to the
Devices
Figure
Stratix IV GX device has 6G ATX PLL
Stratix IV GT device has 6G ATX PLL and 10G ATX PLLs
section.
section.
1–159, the grayed areas show the inactive paths when the PCIe reverse
Compensation
wrclk
TX Phase
FIFO
rdclk
wrclk
Byte Serializer
Receiver Channel PCS
Transmitter Channel PCS
rdclk
8B10B Encoder
Stratix IV Device Handbook Volume 2: Transceivers
Device Datasheet for Stratix IV
Reverse Parallel
Loopback Path
Device Datasheet for Stratix IV
Transmitter Channel
Receiver Channel
PMA
PMA
1–195
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