EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 767
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Instances in Multiple Transceiver Blocks
Combining Transceiver Instances in Multiple Transceiver Blocks
February 2011 Altera Corporation
Figure 3–4
Figure 3–4. Combined Transceiver Instances After Compilation for Example 3
The method to instantiate multiple transceiver channels using a single ALTGX
instance is described in
following section describes the method to instantiate multiple transceiver channels
using multiple transceiver blocks.
When you create a transceiver instance that has more than four transceiver channels
(assuming that the instance is created in non-Basic (PMA Direct) functional mode
which requires regular channels), the Quartus II software attempts to combine the
transceiver channels in multiple transceiver blocks. This is shown in the following
examples.
shows the transceiver channel instances after compilation.
“Creating Transceiver Channel Instances” on page
Inst 2
Effective Data Rate: 1.25 Gbps
Inst 3
Effective Data Rate: 2 Gbps
Inst 0
Effective Data Rate: 3.25 Gbps
Inst 1
Effective Data Rate: 2.5 Gbps
Transceiver Channel1
Transceiver Channel0
TX Loc Div: /1
TX Loc Div: /1
Transceiver Block
TX Channel
RX Channel
Base Data Rate:
Base Data Rate:
RX Channel
TX Channel
3.125 Gbps
1.25 Gbps
CMU PLL
CMU PLL
Stratix IV Device Handbook Volume 2: Transceivers
3–3. The
3–13
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