EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 514
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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- Download datasheet (32Mb)
1–70
Table 1–31. Word Aligner Options Available in Basic Single-Width and Double-Width Modes
Stratix IV Device Handbook Volume 2: Transceivers
Basic
Double-
Width
Note to
(1) For more information about word aligner operation, refer to
Functional
Mode
Width Mode” on page
Table
1–31:
20-bit
PMA-PCS
Interface
Width
16-bit
1–66.
Word Alignment
Alignment
Alignment
Manual
Bit-Slip
Manual
Bit-Slip
Mode
8-, 16-, and
8-, 16-, and
7-, 10-, and
7-, 10-, and
Alignment
Pattern
Length
32-bit
32-bit
20-bit
20-bit
Word
“Word Aligner in Single-Width Mode” on page 1–60
rx_enapatternalign
Rising Edge
Rising Edge
Sensitivity
Sensitive
Sensitive
N/A
N/A
Chapter 1: Transceiver Architecture in Stratix IV Devices
Stays high after
the word aligner
aligns to the
word alignment
pattern. Goes low
on receiving a
rising edge on
rx_enapattern
align until a
new word
alignment pattern
is received.
Stays high after
the word aligner
aligns to the
word alignment
pattern. Goes low
on receiving a
rising edge on
rx_enapattern
align until a
new word
alignment pattern
is received.
rx_syncstatus
Behavior
N/A
N/A
February 2011 Altera Corporation
(Note 1)
Transceiver Block Architecture
and
“Word Aligner in Double-
(Part 2 of 2)
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
rx_patterndetect
Behavior
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