EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 62

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–6
Figure 3–5. Output Latch Asynchronous Clear Waveform
Stratix IV Device Handbook Volume 1
Mixed Width Support
Asynchronous Clear
aclr at latch
outclk
aclr
f
1
q
Figure 3–4
Figure 3–4. Address Clock Enable During the Write Cycle Waveform
M9K and M144K memory blocks support mixed data widths inherently. MLABs can
support mixed data widths through emulation using the Quartus II software. When
using simple dual-port, true dual-port, or FIFO modes, mixed width support allows
you to read and write different data widths to a memory block. For more information
about the different widths supported per memory mode, refer to
on page
MLABs do not support mixed-width FIFO mode.
Stratix IV TriMatrix memory blocks support asynchronous clears on output latches
and output registers. Therefore, if your RAM is not using output registers, you can
still clear the RAM outputs using the output latch asynchronous clear.
shows a waveform of the output latch asynchronous clear function.
You can selectively enable asynchronous clears per logical memory using the
Quartus II RAM MegaWizard Plug-In Manager.
For more information, refer to the
latched address
(inside memory)
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
3–8.
addressstall
wraddress
shows the address clock enable waveform during the write cycle.
inclock
wren
data
an
XX
a0
00
XX
a0
a1
01
Internal Memory (RAM and ROM) User
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
XX
01
02
a2
XX
XX
XX
a1
02
a3
03
00
04
a4
February 2011 Altera Corporation
a4
03
“Memory Modes”
a5
05
04
Figure 3–5
a5
Guide.
05
a6
06
Overview