EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 619

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–141. SONET/SDH OC-12 Datapath
Figure 1–142. SONET/SDH OC-48 Datapath
February 2011 Altera Corporation
tx_coreclk
rx_coreclk
tx_coreclk
rx_coreclk
FPGA
Fabric
Fabric
FPGA
FPGA Fabric-Transmitter
SONET/SDH OC-12 Datapath
Figure 1–141
mode.
SONET/SDH OC-48 Datapath
Figure 1–142
mode.
FPGA Fabric-Receiver
FPGA Fabric-Transmitter
FPGA Fabric-Receiver
Interface Clock
Interface Clock
Interface Clock
Interface Clock
shows the transceiver datapath when configured in SONET/SDH OC-12
shows the transceiver datapath when configured in SONET/SDH OC-48
tx_clkout
rx_clkout
Compensation
RX Phase
rx_clkout
Compensation
tx_clkout
FIFO
RX Phase
Compensation
FIFO
wrclk
TX Phase
Compensation
wrclk
FIFO
TX Phase
FIFO
rdclk
rdclk
Ordering
Byte
Transmitter Channel PCS
Low-Speed Parallel Clock
wrclk
Serializer
Transmitter Channel PCS
Receiver Channel PCS
Parallel Recovered Clock
Byte De-
serializer
Byte
/2
/2
Low-Speed Parallel Clock
Receiver Channel PCS
rdclk
Recovered Clock
Aligner
Word
Parallel
Aligner
Word
Stratix IV Device Handbook Volume 2: Transceivers
Serializer
Receiver Channel PMA
Transmitter Channel PMA
De-
Receiver Channel PMA
Transmitter Channel PMA
Serializer
Serializer
De-
Serializer
Divider
Local
Clock
Divider
Clock
Local
CDR
High-Speed
Serial Clock
CDR
High-Speed
Serial Clock
1–175