EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 197
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
February 2011 Altera Corporation
A pair of RUP and RDN pins are available in a given I/O bank and are shared for
series- and parallel-calibrated termination. The RUP and RDN pins share the same V
and GND, respectively, with the I/O bank where they are located. The RUP and RDN
pins are dual-purpose I/Os and function as regular I/Os if you do not use the
calibration circuit.
For calibration, the connections are as follows:
■
■
For on-chip parallel termination, the connections are as follows:
■
■
On-Chip Series (R
Stratix IV devices support driver-impedance matching to provide the I/O driver with
controlled output impedance that closely matches the impedance of the transmission
line. As a result, you can significantly reduce reflections. Stratix IV devices support
on-chip series termination for single-ended I/O standards
The R
Typical R
strength is no longer selectable.
Figure 6–18. On-Chip Series Termination Without Calibration
To use on-chip termination for the SSTL Class I standard, you must select the 50- Ω
on-chip series termination setting, thus eliminating the external 25- Ω R
the 50- Ω transmission line). For the SSTL Class II standard, you must select the 25- Ω
on-chip series termination setting (to match the 50- Ω transmission line and the
near-end external 50- Ω pull-up to V
The RUP pin is connected to V
resistor for an on-chip series termination value of 25- Ω or 50- Ω , respectively.
The RDN pin is connected to GND through an external 25- Ω ±1% or 50- Ω ±1%
resistor for an on-chip series termination value of 25- Ω or 50- Ω , respectively.
The RUP pin is connected to V
The RDN pin is connected to GND through an external 50- Ω ±1% resistor.
S
shown in
S
values are 25 Ω and 50 Ω . When you select matching impedance, current
Series Termination
Figure 6–18
Stratix IV Driver
S
) Termination Without Calibration
V
GND
CCIO
is the intrinsic impedance of the output transistors.
R
R
S
S
CCIO
CCIO
TT
).
through an external 25- Ω ±1% or 50- Ω ±1%
through an external 50- Ω ±1% resistor.
Z
O
= 50 Ω
(Figure
Stratix IV Device Handbook Volume 1
Receiving
Device
6–18).
S
(to match
CCIO
6–25
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