EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 30
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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1–16
Table 1–5. Stratix IV E Device Package Options
Table 1–6. Stratix IV E Device On-Package Decoupling Information
Table 1–7. Stratix IV GT Device Features (Part 1 of 2)
Stratix IV Device Handbook Volume 1
EP4SE230
EP4SE360
EP4SE530
EP4SE820
Notes to
(1) Device packages in the same column and marked under the same arrow sign have vertical migration capability.
(2) The 780-pin EP4SE360 device is available only in the 33 mm × 33 mm Hybrid flip chip package.
(3) The 1152-pin and 1517-pin for EP4SE530 and EP4SE820 devices are available only in the 42.5 mm × 42.5 mm Hybrid flip chip package.
(4) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information, refer to the
(5) Devices listed in this column do not have on-package decoupling capacitors.
(6) Devices listed in this column have on-package decoupling capacitors. For more information about on-package decoupling capacitor value for
Note to
(1)
Feature
Package Pin Count
ALMs
LEs
Total Transceiver
Channels
Device
Information Datasheet for Altera
each device, refer to
Table 1–6
devices, contact
Table
Table
EP4SE360
EP4SE530
EP4SE820
1–6:
refers to production devices on-package decoupling. For more information about decoupling design of engineering sample (ES)
1–5:
(29 mm × 29 mm) (4),
Altera Technical
Ordering Information
Table
H29
Table 1–5
Table 1–6
Table 1–7
F780
F29
—
—
(5)
EP4S40G2
1–6.
(2)
228,000
91,200
1517
36
Devices.
Support.
summarizes the Stratix IV E device package options.
lists the Stratix IV E on-package decoupling information.
lists the Stratix IV GT device features.
EP4S40G5
212,480
531,200
(35 mm × 35 mm) (4),
H35
H40
H35
H40
F35
F43
F43
1517
36
(Note 1)
H35
H35
F1152
F35
—
(6)
EP4S100G2
(3)
(3)
228,000
91,200
1517
36
4× 1 uF + 4× 470 nF
4× 1 uF + 4× 470 nF
4× 1 uF + 4× 470 nF
(Note 1)
EP4S100G3
(40 mm × 40 mm)
116,480
291,200
1932
V
48
CC
Chapter 1: Overview for the Stratix IV Device Family
H40
H40
F1517
—
—
(3)
(3)
EP4S100G4
141,440
353,600
1932
48
(6)
February 2011 Altera Corporation
(42.5 mm × 42.5 mm)
10 nF per bank
10 nF per bank
10 nF per bank
1517
36
EP4S100G5
Architecture Features
V
CCIO
212,480
531,200
F1760
F43
F43
—
—
Package
1932
48
(6)
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