EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 712

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–40
Figure 2–23. Receiver Datapath Clocking in Non-Bonded Configurations Without Rate Matcher
Note to
(1) The red lines represent the FPGA fabric-Transceiver interface clock, the green lines represent the parallel recovered clock, and the blue lines
Stratix IV Device Handbook Volume 2: Transceivers
represent the serial recovered clock.
rx_coreclk[2]
rx_coreclk[3]
rx_coreclk[0]
rx_coreclk[1]
Figure
FPGA
Fabric
2–23:
FPGA Fabric-Transceiver
FPGA Fabric-Transceiver
FPGA Fabric-Transceiver
FPGA Fabric-Transceiver
Interface Clock
Interface Clock
Interface Clock
Interface Clock
Figure 2–23
without rate matcher.
In non-bonded configurations without rate matcher, the CDR in each receiver channel
recovers the serial clock from the received data. The serial recovered clock is divided
within the receiver PMA to generate the parallel recovered clock. The deserializer
uses the serial recovered clock in the receiver PMA. The parallel recovered clock and
deserialized data is forwarded to the receiver PCS. The parallel recovered clock in
each channel clocks the word aligner and 8B/10B decoder (if enabled).
hard IP
hard IP
hard IP
hard IP
PCIe
PCIe
PCIe
PCIe
Interface
rx_clkout[2]
Interface
Interface
Interface
rx_clkout[1]
rx_clkout[3]
rx_clkout[0]
PIPE
PIPE
PIPE
PIPE
shows receiver datapath clocking in non-bonded channel configurations
Compensation
Compensation
Compensation
Compensation
RX Phase
RX Phase
RX Phase
RX Phase
FIFO
FIFO
FIFO
FIFO
Ordering
Ordering
Ordering
Ordering
Byte
Byte
Byte
Byte
De-Serializer
De-Serializer
De-Serializer
De-Serializer
Byte
Byte
Byte
Byte
/2
/2
/2
/2
Ch0 Parallel Recovered Clock
Ch1 Parallel Recovered Clock
Ch3 Parallel Recovered Clock
Ch2 Parallel Recovered Clock
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Decoder
8B/10B
Decoder
Decoder
Decoder
8B/10B
8B/10B
8B/10B
Chapter 2: Transceiver Clocking in Stratix IV Devices
Aligner
Aligner
Aligner
Aligner
Word
Word
Word
Word
Channel 0
Channel 3
Channel 1
Channel 2
Transceiver Channel Datapath Clocking
Serializer
Receiver Channel PMA
Receiver Channel PMA
Serializer
Serializer
Receiver Channel PMA
Serializer
Receiver Channel PMA
De-
De-
De-
De-
February 2011 Altera Corporation
(Note 1)
CDR
CDR
CDR
CDR
Serial Recovered Clock
Serial Recovered Clock
Serial Recovered Clock
Serial Recovered Clock
Input Reference Clock
Input Reference Clock
Input Reference Clock
Input Reference Clock