EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 826
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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4–20
Figure 4–11. Sample Reset Sequence of Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
Notes to
(1) For t
(2) For t
(3) For t
Stratix IV Device Handbook Volume 2: Transceivers
Output Status Signals
CDR Control Signals
Figure
pll_powerdown
LTR_LTD_Manual
LTD_Manual
Reset Signals
pll _ powerdown
rx _analogreset
rx _ locktorefclk
tx _digitalreset
rx _digitalreset
rx _ locktodata
4–11:
rx _ pll _ locked
duration, refer to the
pll _ locked
duration, refer to the
duration, refer to the
busy
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. If you create a
Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with
the receiver CDR in manual lock mode, use the reset sequence shown in
1
t
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
DC and Switching Characteristics for Stratix IV Devices
DC and Switching Characteristics for Stratix IV Devices
2
3
Two parallel clock cycles
4
5
6
7
t
LTR_LTD_Manual (2)
Chapter 4: Reset Control and Power Down in Stratix IV Devices
t
8
8
LTD_Manual (3)
chapter.
chapter.
chapter.
9
February 2011 Altera Corporation
Transceiver Reset Sequences
Figure
4–11.
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