EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 946
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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5–100
Stratix IV Device Handbook Volume 2: Transceivers
Different Dynamic Reconfiguration Modes Involved
1. Channel and CMU PLL reconfiguration mode—used for reconfiguring four
2. Central control unit reconfiguration mode—used for reconfiguring central control
For more information, refer to
on page
.mif Generation
The following .mifs are required for this example:
■
■
For more information, refer to
Various Dynamic Reconfiguration Transactions
The following dynamic reconfiguration transactions are required for this example:
■
■
regular transceiver channels and the CMU0 PLL (in GXBR0) from XAUI mode to
PCIe ×4 mode and vice versa.
1
unit logic used in bonded modes from XAUI mode to PCIe ×4 mode.
One .mif is required to move from XAUI mode to PCIe ×4 mode
Another .mif is required to revert back to XAUI mode from PCIe ×4 mode
.mif write transaction—for more information, refer to
Reconfiguration Mode Details” on page
Alternatively, you may use reduced .mif reconfiguration. Reduced .mifs are
generated using the altgx_diffmifgen.exe command. For more information, refer
to
“Reduced .mif Reconfiguration” on page
5–19.
Use this mode instead of channel reconfiguration with transmitter PLL
select mode because the central clock divider used for bonded modes is
only available in CMU0; therefore, you cannot use the CMU1 PLL as an
alternate TX PLL.
“Transceiver Channel Reconfiguration Mode Details”
“Memory Initialization File (.mif)” on page
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
5–24.
5–24.
“Channel and CMU PLL
Dynamic Reconfiguration Examples
February 2011 Altera Corporation
5–20.
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