EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 659
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Port Lists
Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 4 of 7)
February 2011 Altera Corporation
8B/10B Decoder
rx_ctrldetect
rx_errdetect
rx_disperr
Port Name
Output
Output
Output
Output
Input/
tx_clkout, and
coreclkout for
coreclkout for
Synchronous to
Synchronous to
Synchronous to
rx_clkout or
rx_clkout or
rx_clkout for
bonded modes
rx_clkout for
bonded modes
Clock Domain
coreclkout.
coreclkout.
coreclkout
clock signals
rx_clkout,
non-bonded
non-bonded
modes.
modes.
Receiver control code indicator.
■
■
■
■
Channel Width:
8—rx_ctrldetect = 1
16—rx_ctrldetect = 2
32—rx_ctrldetect = 4
8B/10B code group violation or disparity error
indicator.
■
■
■
8B/10B disparity error indicator port.
■
■
■
Available in configurations with 8B/10B
decoder.
A high level—the associated received code
group is a control (/Kx.y/) code group.
A low level—the associated received code
group is a data (/Dx.y/) code group.
The width of this signal depends on the
following channel width:
Available in configurations with 8B/10B
decoder.
A high level—a code group violation or
disparity error was detected on the
associated received code group. Use with
the rx_disperr signal to differentiate
between a code group violation and/or a
disparity error as follows:
■
■
■
■
Channel Width:
8—rx_errdetect = 1
16—rx_errdetect = 2
32—rx_errdetect = 4
Available in configurations with 8B/10B
decoder.
A high level—a disparity error was detected
on the associated received code group.
Channel Width:
8—rx_disperr = 1
16—rx_disperr = 2
32—rx_disperr = 4
[rx_errdetect: rx_disperr]
2’b00—no error
2’b10—code group violation
2’b11—disparity error or both
Stratix IV Device Handbook Volume 2: Transceivers
Description
Channel
Channel
Channel
Scope
1–215
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