EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 518
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1–74
Stratix IV Device Handbook Volume 2: Transceivers
Figure 1–56
datapath configurations.
Figure 1–56. Receiver Bit Reversal in Double-Width Mode
Because receiver bit reversal is done at the output of the word aligner, a dynamic bit
reversal also requires a reversal of the word alignment pattern. As a result, the
Receiver Bit Reversal feature is dynamic only if the receiver is dynamically
reconfigurable (it allows changing the word alignment pattern dynamically) or uses
manual bit slip alignment mode (no word alignment pattern). The Receiver Bit
Reversal feature is static in all other Basic mode configurations. You can enable this
feature using the MegaWizard Plug-In Manager. In configurations where the Receiver
Bit Reversal feature is dynamic, an rx_revbitordwa port is available to control the bit
reversal dynamically. A high on the rx_revbitordwa port reverses the bit order at the
input of the word aligner.
shows the receiver bit reversal feature in Basic double-width 20-bit wide
Output of Word Aligner
before RX bit reversal
D[19]
D[18]
D[17]
D[16]
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
rx_revbitordwa = high
Chapter 1: Transceiver Architecture in Stratix IV Devices
Output of Word Aligner
after RX bit reversal
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
D[16]
D[17]
D[18]
D[19]
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
February 2011 Altera Corporation
Transceiver Block Architecture
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