XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 102

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Powering Spartan-3E FPGAs
Voltage Supplies
Like Spartan-3 FPGAs, Spartan-3E FPGAs have multiple
voltage supply inputs, as shown in
supply inputs for internal logic functions, V
Table 58: Spartan-3E Voltage Supplies
In a 3.3V-only application, all four V
3.3V. However, Spartan-3E FPGAs provide the ability to
bridge between different I/O voltages and standards by
applying different voltages to the V
banks. Refer to
can be intermixed within a single I/O bank.
Each I/O bank also has an separate, optional input voltage
reference supply, called VREF. If the I/O bank includes an
I/O standard that requires a voltage reference such as
HSTL or SSTL, then all VREF pins within the I/O bank must
be connected to the same voltage.
Voltage Regulators
Various power supply manufacturers offer complete power
solutions for Xilinx FPGAs including some with integrated
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
VCCAUX
VCCO_0
VCCO_1
VCCO_2
VCCO_3
VCCINT
Supply
Input
R
Internal core supply voltage. Supplies all internal logic functions such as
CLBs, block RAM, multipliers, etc. Input to Power-On Reset (POR) circuit.
Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs),
differential drivers, dedicated configuration pins, JTAG interface. Input to
Power-On Reset (POR) circuit.
Supplies the output buffers in I/O Bank 0, the bank along the top edge of the
FPGA.
Supplies the output buffers in I/O Bank 1, the bank along the right edge of the
FPGA. In
connects to the save voltage as the Flash PROM.
Supplies the output buffers in I/O Bank 2 the bank along the bottom edge of
the FPGA. Connects to the same voltage as the FPGA configuration source.
Input to Power-On Reset (POR) circuit.
Supplies the output buffers in I/O Bank 0, the bank along the top edge of the
FPGA.
I/O Banking Rules
Byte-Wide Peripheral Interface (BPI) Parallel Flash
CCO
Table
for which I/O standards
CCO
supplies connect to
58. There are two
inputs of different
Description
CCINT
www.xilinx.com
and
V
supply input that powers the output buffers within the asso-
ciated I/O bank. All of the V
bank must be connected and must connect to the same
voltage.
three-rail regulators specifically designed for Spartan-3 and
Spartan-3E FPGAs. The
vides links to vendor solution guides and Xilinx power esti-
mation and analysis tools.
Power Distribution System (PDS) Design and
Decoupling/Bypass Capacitors
Good power distribution system (PDS) design is important
for all FPGA designs, but especially so for high performance
applications, greater than 100 MHz. Proper design results in
better overall performance, lower clock and DCM jitter, and
a generally more robust system. Before designing the
printed circuit board (PCB) for the FPGA design, please
review XAPP623: "Power Distribution System (PDS)
Design: Using Bypass/Decoupling Capacitors".
CCAUX
. Each of the four I/O banks has a separate V
Mode,
Xilinx Power Corner
CCO
2.5V, 1.8, 1.5V, or 1.2V.
2.5V, 1.8, 1.5V, or 1.2V.
2.5V, 1.8, 1.5V, or 1.2V.
2.5V, 1.8, 1.5V, or 1.2V.
connections to a specific I/O
Selectable, 3.3V, 3.0V,
Selectable, 3.3V, 3.0V,
Selectable, 3.3V, 3.0V,
Selectable, 3.3V, 3.0V,
Nominal Supply
Functional Description
Voltage
1.2V
2.5V
web site pro-
CCO
95