XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 37

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Table 20: Block RAM Port Signals
30
Address Bus
Data Input Bus
Parity Data
Input(s)
Description
Notes:
1.
2.
3.
4.
Signal
DIA[w
DIB[w
ADDRA[r
ADDRB[r
DIPB[p
w
p
r
The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
DIPA[p
A
A
A
and r
and p
A
B
and w
–p
–p
SSRA
A
A
A
SSRB
B
B
B
CLKA
CLKB
B
WEA
WEB
–1:0]
–1:0]
–1:0]
–1:0]
–1:0]
–1:0]
B
ENA
ENB
B
are integers representing the address bus width at ports A and B, respectively.
are integers that indicate the number of data path lines serving as parity bits.
are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
ADDRA
Port A
Signal
Name
DIPA
DIA
RAMB16_w
(a) Dual-Port
ADDRB
Signal
Port B
Name
DIPB
DIB
A
_w
B
Figure 29: Block RAM Primitives
Direction
DOPA[p
DOA[w
DOPB[p
DOB[w
Input
Input
Input
A
B
A
–p
B
–p
–1:0]
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–1:0]
A
B
–1:0]
–1:0]
The Address Bus selects a memory location for read or write
operations. The width (w) of the port’s associated data path
determines the number of available address lines (r), as per
Table
Data at the DI input bus is written to the RAM location specified
by the address input bus (ADDR) during the active edge of the
CLK input, when the clock enable (EN) and write enable (WE)
inputs are active.
It is possible to configure a port’s DI input bus width (w-p) based
on
of a given port.
Parity inputs represent additional bits included in the data input
path. Although referred to herein as “parity” bits, the parity inputs
and outputs have no special functionality for generating or
checking parity and can be used as additional data bits. The
number of parity bits ‘p’ included in the DI (same as for the DO
bus) depends on a port’s total data path width (w). See
Table
18.
18. This selection applies to both the DI and DO paths
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
SSR
CLK
WE
EN
Function
(b) Single-Port
RAMB16_Sw
Advance Product Specification
DS312-2 (v1.1) March 21, 2005
DOP[p–1:0]
DO[w–p–1:0]
DS312-2_03_021305
Table
18.
R