XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 81

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
74
A[23:0]
D[7:0]
CSO_B
BUSY
CCLK
INIT_B
Pin Name
FPGA Direction
bidirectional I/O
Open-drain
Output
Output
Output
Output
Input
Address
Data Input
Chip Select Output. Active Low.
Busy Indicator. Typically only
used after configuration, if
bitstream option Persist=Yes .
Configuration Clock. Generated
by FPGA internal oscillator.
Frequency controlled by
ConfigRate bitstream generator
option. If CCLK PCB trace is long
or has multiple connections,
terminate this output to maintain
signal integrity.
Initialization Indicator. Active
Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
Description
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Connect to PROM address
inputs. High order address lines
may not be available in all
packages and not all may be
required. Number of address
lines required depends on the
size of the attached Flash PROM.
FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
Only 20 address lines are
available in TQ144 package.
FPGA receives byte-wide data on
these pins in response the
address presented on A[23:0].
Data captured by FPGA
Not used in single FPGA
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. Actively drives.
Not used during configuration but
actively drives.
Not used in single FPGA
applications but actively drives. In
a daisy-chain configuration,
drives the CCLK inputs of all other
FPGAs in the daisy-chain.
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
During Configuration
Advance Product Specification
DS312-2 (v1.1) March 21, 2005
User I/O
User I/O If bitstream
option Persist=Yes ,
becomes part of
SelectMap parallel
peripheral interface.
User I/O
User I/O.
option Persist=Yes ,
becomes part of
SelectMap parallel
peripheral interface.
User I/O If bitstream
option Persist=Yes ,
becomes part of
SelectMap parallel
peripheral interface.
User I/O
After Configuration
If bitstream
R