XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 160

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FG320: 320-ball Fine-pitch Ball Grid
Array
The 320-lead fine-pitch ball grid array package, FG320,
supports three different Spartan-3E FPGAs, including the
XC3S500E, the XC3S1200E, and the XC3S1600E, as
shown in
The FG320 package is an 18 x 18 array of solder balls
minus the four center balls.
Table 24
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
The highlighted rows indicate pinout differences between
the XC3S500E, the XC3S1200E, and the XC3S1600E
FPGAs. The XC3S500E has 18 unconnected balls, indi-
cated as N.C. (No Connection) in
black diamond character ( ) in both
Figure
Table 24: FG320 Package Pinout
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8.
lists all the package pins. They are sorted by bank
Table 24
R
IP
IO
IO
IO
IP
IO
IO
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
XC3S500E Pin Name
and
Figure
8.
Table 24
IO
IO
IO
IO
IO
IO
IO
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
Table 24
XC3S1200E Pin Name
and with the
and in
www.xilinx.com
If the table row is highlighted in tan, then this is an instance
where an unconnected pin on the XC3S500E FPGA maps
to a VREF pin on the XC3S1200E and XC3S1600E FPGA.
If the FPGA application uses an I/O standard that requires a
VREF voltage reference, connect the highlighted pin to the
VREF voltage supply, even though this does not actually
connect to the XC3S500E FPGA. This VREF connection on
the board allows future migration to the larger devices with-
out modifying the printed-circuit board.
All other balls have nearly identical functionality on all three
devices.
migration differences for the FG320 package.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at
Pinout Table
IO
IO
IO
IO
IO
IO
IO
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
http://www.xilinx.com/bvdocs/publications/s3e_pin.zip
XC3S1600E Pin Name
Table 23
summarizes the Spartan-3E footprint
FG320
Ball
A11
D13
E13
B11
A16
B16
C14
D14
A14
B14
B13
A13
E12
F12
G9
A7
A8
C4
Pinout Descriptions
500E: INPUT
500E: INPUT
1200E: I/O
1600E: I/O
1200E: I/O
1600E: I/O
VREF
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
.
39