XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 75

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Power-On Precautions if 3.3V Supply is Last in
Sequence
Spartan-3E FPGAs have a built-in power-on reset (POR)
circuit, as shown in
power supplies
Bank 2 (VCCO_2)
thresholds before beginning the configuration process.
Table 48: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
In many systems, the 3.3V supply feeding the FPGA's
VCCO_2 input is valid before the FPGA's other VCCINT
and VCCAUX supplies, and consequently, there is no issue.
However, if the 3.3V supply feeding the FPGA's VCCO_2
supply is last in the sequence, a potential race occurs
between the FPGA and the SPI Flash PROM, as shown in
Figure
If the FPGA's VCCINT and VCCAUX supplies are already
valid, then the FPGA waits for VCCO_2 to reach its mini-
mum threshold voltage before starting configuration. This
threshold voltage is labeled as V
ranges from approximately 0.4V to 1.0V, substantially lower
than the SPI Flash PROM's minimum voltage. Once all
three FPGA supplies reach their respective Power On
Reset (POR) thresholds, the FPGA starts the configuration
process and begins initializing its internal configuration
memory. Initialization requires approximately 1 ms (T
68
STMicroelectronics
NexFlash
Silicon Storage Technology
Programmable
Microelectronics Corporation
Atmel Corporation
52.
Figure 52: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence
Vendor
FPGA VCCO_2 minimum
—
Power On Reset Voltage
Figure
—
VCCINT, VCCAUX, and VCCO to I/O
to reach their respective power-on
SPI Flash PROM
minimum voltage
(VCCINT, VCCAUX
already valid)
63. The FPGA waits for its three
(V
CCO2T
CCO2T
SPI Flash PROM
3.3V Supply
Part Number
SST25LFxx
Pm25LVxxx
AT45DBxx
M25Pxx
NX25xx
)
in
SPI Flash cannot be selected
Module 3
FPGA initializes configuration
www.xilinx.com
POR
and
memory
Data Sheet Minimum Time from VCC, min. to Select = Low
,
The SPI Flash PROM is powered by the same voltage sup-
ply feeding the FPGA's VCCO_2 voltage input, typically
3.3V. SPI Flash PROMs specify that they cannot be
accessed until their VCC supply reaches its minimum data
sheet voltage, followed by an additional delay. For some
devices, this additional delay is as little as 10 µs as shown in
Table
minimum in
INIT_B, selects the SPI Flash PROM, and starts sending
the appropriate read command. The SPI Flash PROM must
be ready for read operations at this time.
If the 3.3V supply is last in the sequence and does not ramp
fast enough, or if the SPI Flash PROM cannot be ready
when required by the FPGA, delay the FPGA configuration
process by holding either the FPGA's PROG_B input or
INIT_B input Low, as highlighted in
FPGA when the SPI Flash PROM is ready. For example, a
simple R-C delay circuit attached to the INIT_B pin forces
the FPGA to wait for a preselected amount of time. Alter-
nately, a Power Good signal from the 3.3V supply or a sys-
tem reset signal accomplishes the same purpose. Use an
open-drain or open-collector output when driving PROG_B
or INIT_B.
T
PROM CS
Symbol
SPI Flash
delay
PU-READ
(T
T
T
T
VCS
POR
VSL
VSL
48. For other vendors, it is as much as 20 ms.
(t
Time
)
VSL
)
Module
SPI Flash available for
read operations
SPI Flash PROM
access otherwise delay
FPGA accesses
SPI Flash PROM must
FPGA configuration
3), after which the FPGA deasserts
be ready for FPGA
Value
10
10
10
50
20
Advance Product Specification
DS312-2 (v1.1) March 21, 2005
DS312-2_50b_022405
Figure
51. Release the
Units
ms
µs
µs
µs
µs
R