XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 134

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CP132 Footprint
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
22
0
2
0
G
M
A
B
C
D
E
H
K
N
P
F
J
L
I/O: Unrestricted,
general-purpose user I/O
INPUT: Unrestricted,
general-purpose input pin
CONFIG: Dedicated
configuration pins
N.C.: Not connected
PROG_B
VCCAUX
VCCO_3
LHCLK3
LHCLK2
LHCLK5
L01N_3
L03N_3
L05P_3
L05N_3
L06N_3
L08P_3
L09N_3
L01N_2
L02P_2
R
IRDY2
INIT_B
DOUT
GND
BUSY
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
VCCINT
VCCINT
VREF_3
VCCO_3
LHCLK6
L01P_3
L02N_3
L03P_3
INPUT
L04N_3
LHCLK1
L07P_3
L08N_3
L01P_2
CSO_B
L02N_2
CSI_B
MOSI
GND
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
VCCINT
VCCO_2
HSWAP
LHCLK0
LHCLK4
L11N_0
LHCLK7
VREF_3
VREF_2
L11P_0
L02P_3
L04P_3
L06P_3
L07N_3
L09P_3
TRDY2
INPUT
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
GCLK12
GCLK13
L10N_0
L10P_0
L03P_2
L03N_2
GND
I/O
I/O
I/O
I/O
I/O
D5
D7
D6
4
Figure 3: CP132 Package Footprint (top view)
VCCAUX
GCLK14
GCLK15
L09P_0
L09N_0
L04P_2
L04N_2
GND
I/O
I/O
I/O
I/O
D4
D3
5
42
16
16
4
RDWR_B
VCCO_0
VREF_0
L08P_0
L08N_0
L05P_2
L05N_2
L06P_2
INPUT
GCLK0
INPUT
GCLK1
GCLK2
I/O
I/O
I/O
M2
D2
6
DUAL: Configuration pin, then
possible user I/O
GCLK: User I/O, input, or
global buffer input
JTAG: Dedicated JTAG port
pins
GND: Ground
Bank 2
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GCLK10
GCLK11
L07P_0
L07N_0
L06N_2
GCLK3
GND
GND
I/O
I/O
I/O
I/O
M1
D1
7
Bank 0
VCCO_2
INPUT
L06P_0
INPUT
L06N_0
L07N_2
L07P_2
GCLK9
GCLK8
GND
I/O
DIN
I/O
M0
D0
8
VCCAUX
L05N_0
GCLK7
L05P_0
GCLK6
L04N_0
GCLK5
L08N_2
L08P_2
A22
A23
I/O
I/O
I/O
I/O
I/O
9
VCCO_0
L09N_2
L04P_0
L09P_2
GCLK4
GND
GND
A20
A21
10
I/O
I/O
I/O
VCCINT
VREF_0
L03N_0
L10N_2
L03P_0
L10P_2
VREF_2
VS1
VS2
A18
A19
11
I/O
I/O
I/O
I/O
I/O
8
8
6
4
VCCINT
VCCAUX
RHCLK5
RHCLK1
VREF_1
L02N_0
L02P_0
L01N_0
L09N_1
L06N_1
L04N_1
L02P_1
L11N_2
L11P_2
INPUT
VREF: User I/O or input
voltage reference for bank
VCCO: Output voltage supply
for bank
VCCINT: Internal core supply
voltage (+1.2V)
VCCAUX: Auxiliary supply
voltage (+2.5V)
GND
CCLK
LDC0
VS0
I/O
I/O
I/O
I/O
A14
I/O
A17
12
I/O
I/O
I/O
I/O
I/O
A0
A5
A9
RHCLK7
RHCLK4
RHCLK2
VCCO_1
VREF_1
L01P_0
L10N_1
L09P_1
L08N_1
L07N_1
L06P_1
L05P_1
L03P_1
L02N_1
L01P_1
DONE
IRDY1
LDC2
TCK
HDC
I/O
I/O
I/O
A12
I/O
A13
A16
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A1
A3
A6
A8
Pinout Descriptions
VCCINT
VCCO_1
RHCLK6
RHCLK3
RHCLK0
DS312-4_07_031105
L10P_1
L08P_1
L07P_1
L05N_1
L04P_1
L03N_1
L01N_1
TRDY1
LDC1
GND
GND
GND
TMS
A10
A11
A15
14
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A2
A
A
4
7
13