XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 86

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Similarly, the general FPGA application could trigger a
MultiBoot event at any time to reload the diagnostics design.
In another potential application, the initial design loaded into
the FPGA image contains a “golden” or “fail-safe” configura-
tion image, which then communicates with the outside world
and checks for a newer image. If there is a new configura-
tion revision and the new image verifies as good, the
“golden” configuration triggers a MultiBoot event to load the
new image.
When a MultiBoot event is triggered, the FPGA then again
drives its configuration pins as described in
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
First Configuration
Parallel Flash PROM
Diagnostics
R
Application
Application
User Area
General
FPGA
FPGA
Figure 57: Use MultiBoot to Load Alternate Configuration Images
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0
> 300 ns
Table
51. How-
STARTUP_SPARTAN3E
GSR
GTS
MBT
CLK
www.xilinx.com
ever, the FPGA does not assert the PROG_B pin. The sys-
tem design must ensure that no other device drives on
these same pins during the reconfiguration process. The
FPGA’s DONE, LDC[2:0], or HDC pins can temporarily dis-
able any conflicting drivers during reconfiguration.
Slave Parallel Mode
In Slave Parallel mode (M[2:0] = <1:1:0>), an external host
such as a microprocessor or microcontroller writes
byte-wide configuration data into the FPGA, using a typical
peripheral interface as shown in
Reconfigure
Second Configuration
Parallel Flash PROM
Diagnostics
Application
Application
User Area
Figure
General
FPGA
FPGA
Functional Description
58.
DS312-2_51_021405
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0
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