XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 148

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FT256: 256-ball Fine-pitch, Thin Ball
Grid Array
The 256-lead fine-pitch, thin ball grid array package, FT256,
supports three different Spartan-3E FPGAs, including the
XC3S250E, the XC3S500E, and the XC3S1200E.
Table 19
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
The highlighted rows indicate pinout differences between
the XC3S250E, the XC3S500E, and the XC3S1200E
FPGAs. The XC3S250E has 18 unconnected balls, indi-
cated as N.C. (No Connection) in
black diamond character ( ) in both
Figure
Table 19: FT256 Package Pinout
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7.
lists all the package pins. They are sorted by bank
R
IO
IO
IO
IP
IP
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
IO_L08N_0/GCLK5
IO_L08P_0/GCLK4
IO_L09N_0/GCLK7
XC3S250E Pin Name
Table 19
IO
IO
IO
IP
IP
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
IO_L08N_0/GCLK5
IO_L08P_0/GCLK4
IO_L09N_0/GCLK7
Table 19
XC3S500E Pin Name
and with the
and in
www.xilinx.com
If the table row is highlighted in tan, then this is an instance
where an unconnected pin on the XC3S250E FPGA maps
to a VREF pin on the XC3S500E and XC3S1200E FPGA. If
the FPGA application uses an I/O standard that requires a
VREF voltage reference, connect the highlighted pin to the
VREF voltage supply, even though this does not actually
connect to the XC3S250E FPGA. This VREF connection on
the board allows future migration to the larger devices with-
out modifying the printed-circuit board.
All other balls have nearly identical functionality on all three
devices.
migration differences for the FT256 package.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at
Pinout Table
IO
IO
IO
IO
IO
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
IO_L08N_0/GCLK5
IO_L08P_0/GCLK4
IO_L09N_0/GCLK7
http://www.xilinx.com/bvdocs/publications/s3e_pin.zip
XC3S1200E Pin Name
Table 23
summarizes the Spartan-3E footprint
FT256
Ball
A12
B10
A14
B14
A13
B13
E11
D11
B11
C11
E10
D10
D9
A7
B4
B6
F9
E9
A9
Pinout Descriptions
250E: INPUT
500E: INPUT
250E: INPUT
500E: INPUT
1200E: I/O
1200E: I/O
VREF
VREF
VREF
GCLK
GCLK
GCLK
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
.
27