XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 88

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Alternatively, the
bidirectional SelectMAP configuration interface is available
after configuration. To continue using SelectMAP mode, set
the Persist bitstream generator option to Yes . The external
host can then read and verify configuration data.
Table 55: Slave Parallel Mode Connections
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
HSWAP
M[2:0]
D[7:0]
BUSY
CSI_B
RDWR_B
CCLK
LDC[2:0]
HDC
Pin Name
R
FPGA Direction
Output
Output
Output
Input
Input
Input
Input
Input
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank V
0: Pull-ups during configuration
1: No pull-ups
Mode Select. Selects the FPGA
configuration mode.
Data Input.
Busy Indicator.
Chip Select Input. Active Low.
Read/Write Control. Active Low
write enable.
Configuration Clock. If CCLK
PCB trace is long or has multiple
connections, terminate this output
to maintain signal integrity.
Low During Configuration.
High During Configuration.
Description
CCO
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input.
The Slave Parallel mode is also used with BPI mode to cre-
ate multi-FPGA daisy-chains. The lead FPGA is set for BPI
mode configuration; all the downstream daisy-chain FPGAs
are set for Slave Parallel configuration, as highlighted in
Figure
Drive at valid logic level
throughout configuration.
M2 = 1, M1 = 1, M0 = 0 Sampled
when INIT_B goes High.
Byte-wide data provided by host.
FPGA captures data on rising
CCLK edge.
If CCLK frequency is < 50 MHz,
this pin may be ignored. When
High, indicates that the FPGA is
not ready to receive additional
configuration data. Host must
hold data an additional clock
cycle.
Must be Low throughout
configuration.
Must be Low throughout
configuration.
External clock.
These pins are not used during
configuration. Low throughout
configuration.
This pin is not used during
configuration. High throughout
configuration.
56.
During Configuration
Functional Description
User I/O
User I/O
User I/O. If bitstream
option Persist=Yes ,
becomes part of
SelectMap parallel
peripheral interface.
User I/O. If bitstream
option Persist=Yes ,
becomes part of
SelectMap parallel
peripheral interface.
User I/O. If bitstream
option Persist=Yes ,
becomes part of
SelectMap parallel
peripheral interface.
User I/O. If bitstream
option Persist=Yes ,
becomes part of
SelectMap parallel
peripheral interface.
User I/O If bitstream
option Persist=Yes ,
becomes part of
SelectMap parallel
peripheral interface.
User I/O
User I/O
After Configuration
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