XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 49

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SSTL3_I
A sample circuit illustrating a valid termination technique for
SSTL3_I appears in
appear in
Table 28: SSTL3_I Voltage Specifications
SSTL3_II
A sample circuit illustrating a valid termination technique for
SSTL3_II appears in
appear in
DS022-2 (v2.8) January 16, 2006
Production Product Specification
Notes:
1.
2.
V
V
V
V
V
V
V
I
I
OH
OL
OH
OL
CCO
REF
TT
IH
IL
at V
V
V
= V
= V
at V
= V
= V
= V
IH
IL
= 0.45 × V
minimum does not conform to the formula
maximum is V
OL
REF
REF
REF
OH
REF
Figure 50: Terminated SSTL3 Class II
REF
Figure 49: Terminated SSTL3 Class I
Table
Table
SSTL3 Class II
(mA)
V
Parameter
R
(mA)
– 0.2
CCO
+ 0.2
V
– 0.6
SSTL3 Class I
+ 0.6
CCO
28.
29.
= 3.3V
CCO
= 3.3V
25Ω
CCO
25Ω
Figure
Figure
V
50Ω
+ 0.3
TT
V
V
REF
= 1.5V
REF
49. DC voltage specifications
50. DC voltage specifications
= 1.5V
Z = 50
= 1.5V
50Ω
V
Z = 50
TT
50Ω
V
−0.3
= 1.5V
Min
TT
3.0
1.3
1.3
1.5
1.9
−8
8
x133_13_111699
-
= 1.5V
x133_14_111699
(2)
Typ
3.3
1.5
1.5
1.7
1.3
-
-
-
-
3.9
Max
3.6
1.7
1.7
1.5
1.1
www.xilinx.com
-
-
-
(1)
Table 29: SSTL3_II Voltage Specifications
SSTL2_I
A sample circuit illustrating a valid termination technique for
SSTL2_I appears in
appear in
Table 30: SSTL2_I Voltage Specifications
Notes:
1.
2.
Notes:
1.
2.
3.
V
V
V
V
V
V
V
I
I
V
V
V
V
V
V
V
I
I
OH
OL
OH
OL
OH
OL
OH
OL
CCO
REF
TT
IH
IL
CCO
REF
TT
IH
IL
= V
at V
at V
V
V
N must be greater than or equal to -0.04 and less than or
equal to 0.04.
V
V
= V
= V
= V
= V
at V
= V
at V
= V
= V
= V
IH
IL
= V
IH
IL
Virtex™-E 1.8 V Field Programmable Gate Arrays
= 0.45 × V
= 0.5 × V
REF
minimum does not conform to the formula
minimum does not conform to the formula.
OL
maximum is V
OL
maximum is V
REF
REF
REF
REF
REF
REF
REF
OH
OH
REF
REF
Figure 51: Terminated SSTL2 Class I
Table
Parameter
(mA)
(mA)
Parameter
– 0.2
(mA)
(mA)
– 0.18
– 0.8
– 0.61
+ 0.2
+ 0.18
SSTL2 Class I
+ N
+ 0.8
+ 0.61
V
CCO
30.
CCO
(1)
CCO
= 2.5V
25Ω
CCO
CCO
Figure
+ 0.3
+ 0.3.
V
REF
51. DC voltage specifications
Z = 50
= 1.25V
50Ω
V
−0.3
TT
1.15
1.11
1.33
1.76
−7.6
Min
2.3
7.6
−0.3
= 1.25V
-
Min
−16
1.5
2.1
3.0
1.3
1.3
16
(3)
-
(2)
xap133_15_011000
1.25
1.25
1.43
1.07
Typ
2.5
Typ
3.3
1.5
1.5
1.7
1.3
-
-
-
-
-
-
-
-
Module 2 of 4
3.9
3.0
Max
Max
1.35
1.39
1.17
0.74
3.6
1.7
1.7
1.5
0.9
2.7
-
-
-
-
-
-
(1)
(2)
43