XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 55

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 42: Input Library Macros
Creating LVDS Output Buffers
LVDS output buffers can be placed in a wide number of IOB
locations. The exact locations are dependent on the pack-
age used. The Virtex-E package information lists the possi-
ble locations as IO_L#P for the P-side and IO_L#N for the
N-side, where # is the pair number.
HDL Instantiation
Both output buffers are required to be instantiated in the
design and placed on the correct IO_L#P and IO_L#N loca-
tions. The IOB must have the same net source the following
pins, clock (C), set/reset (SR), output (O), output clock
enable (OCE). In addition, the output (O) pins must be
inverted with respect to each other, and if output registers
are used, the INIT states must be opposite values (one
HIGH and one LOW). Failure to follow these rules leads to
DRC errors in software.
VHDL Instantiation
DS022-2 (v2.8) January 16, 2006
Production Product Specification
IBUFDS_FD_LVDS
IBUFDS_FDE_LVDS
IBUFDS_FDC_LVDS
IBUFDS_FDCE_LVDS
IBUFDS_FDP_LVDS
IBUFDS_FDPE_LVDS
IBUFDS_FDR_LVDS
IBUFDS_FDRE_LVDS
IBUFDS_FDS_LVDS
IBUFDS_FDSE_LVDS
IBUFDS_LD_LVDS
IBUFDS_LDE_LVDS
IBUFDS_LDC_LVDS
IBUFDS_LDCE_LVDS
IBUFDS_LDP_LVDS
IBUFDS_LDPE_LVDS
data0_p
(I=>data_int(0),
data0_inv: INV
(I=>data_int(0),
data0_n
(I=>data_n_int(0), O=>data_n(0));
Name
R
: OBUF_LVDS port map
: OBUF_LVDS port map
I, IB, CE, C, CLR
I, IB, CE, C, PRE
I, IB, GE, G, CLR
I, IB, GE, G, PRE
I, IB, CE, C, R
I, IB, CE, C, S
I, IB, C, PRE
I, IB, G, CLR
I, IB, G, PRE
O=>data_p(0));
O=>data_n_int(0));
I, IB, C, CLR
I, IB, CE, C
I, IB, GE, G
I, IB, C, R
I, IB, C, S
port map
I, IB, C
I, IB, G
Inputs
Outputs
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
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Verilog Instantiation
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the .ucf or .ncf file.
Synchronous vs. Asynchronous Outputs
If the outputs are synchronous (registered in the IOB) then
any IO_L#P|N pair can be used. If the outputs are asynchro-
nous (no output register), then they must use one of the
pairs that are part of the same IOB group at the end of a
ROW or COLUMN in the device.
The LVDS pairs that can be used as asynchronous outputs
are listed in the Virtex-E pinout tables. Some pairs are
marked as asynchronous-capable for all devices in that
package, and others are marked as available only for that
device in the package. If the device size might change at
some point in the product lifetime, then only the common
pairs for all packages should be used.
Adding an Output Register
All LVDS buffers can have an output register in the IOB. The
output registers must be in both the P-side and N-side IOBs.
All the normal IOB register options are available (FD, FDE,
FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,
LDE, LDC, LDCE, LDP, LDPE). The register elements can
be inferred or explicitly instantiated in the HDL code.
Special care must be taken to insure that the D pins of the
registers are inverted and that the INIT states of the regis-
ters are opposite. The clock pin (C), clock enable (CE) and
set/reset (CLR/PRE or S/R) pins must connect to the same
source. Failure to do this leads to a DRC error in the soft-
ware.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs.
To improve design coding times VHDL and Verilog synthe-
sis macro libraries have been developed to explicitly create
these structures. The output library macros are listed in
Table
nal net connections.
OBUF_LVDS data0_p
.O(data_p[0]));
INV
.O(data_n_int[0]);
OBUF_LVDS data0_n
.O(data_n[0]));
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
43. The O and OB inputs to the macros are the exter-
Virtex™-E 1.8 V Field Programmable Gate Arrays
data0_inv (.I(data_int[0],
(.I(data_int[0]),
(.I(data_n_int[0]),
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