XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 53

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Termination Resistor Packs
Resistor packs are available with the values and the config-
uration required for LVDS and LVPECL termination from
Bourns, Inc., as listed in Table. For pricing and availability,
please contact Bourns directly at
Table 40: Bourns LVDS/LVPECL Resistor Packs
LVDS Design Guide
The SelectI/O library elements have been expanded for Vir-
tex-E devices to include new LVDS variants. At this time all
of the cells might not be included in the Synthesis libraries.
The 2.1i-Service Pack 2 update for Alliance and Foundation
software includes these cells in the VHDL and Verilog librar-
ies. It is necessary to combine these cells to create the
P-side (positive) and N-side (negative) as described in the
input, output, 3-state and bidirectional sections.
DS022-2 (v2.8) January 16, 2006
Production Product Specification
CAT16−LV2F6
CAT16−LV4F12
CAT16−PC2F6
CAT16−PC4F12
CAT16−PT2F2
CAT16−PT4F4
Part Number
IBUFG_LVDS
IBUF_LVDS
R
I
I
Figure 58: LVDS elements
O
O
LVDS/LVPECL
LVDS/LVPECL
I/O Standard
LVPECL
LVPECL
LVDS
LVDS
OBUF_LVDS
OBUFT_LVDS
T
I
I
O
O
http://www.bourns.com
Receiver
Receiver
Term.
Driver
Driver
Driver
Driver
for:
IOBUF_LVDS
O
T
I
x133_22_122299
IO
Pairs/
Pack
2
4
2
4
2
4
Pins
www.xilinx.com
16
16
16
8
8
8
.
Creating LVDS Global Clock Input Buffers
Global clock input buffers can be combined with adjacent
IOBs to form LVDS clock input buffers. P-side is the GCLK-
PAD location; N-side is the adjacent IO_LVDS_DLL site.
Table 41: Global Clock Input Buffer Pair Locations
HDL Instantiation
Only one global clock input buffer is required to be instanti-
ated in the design and placed on the correct GCLKPAD
location. The N-side of the buffer is reserved and no other
IOB is allowed to be placed on this location.
In the physical device, a configuration option is enabled that
routes the pad wire to the differential input buffer located in
the GCLKIOB. The output of this buffer then drives the out-
put of the GCLKIOB cell. In EPIC it appears that the second
buffer is unused. Any attempt to use this location for another
purpose leads to a DRC error in the software.
VHDL Instantiation
Verilog Instantiation
Location constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.
GCLKPAD3 can also be replaced with the package pin
name such as D17 for the BG432 package.
FG1156
HQ240
CS144
PQ240
BG352
BG432
BG560
FG256
FG456
FG676
FG680
FG860
FG900
Pkg
gclk0_p : IBUFG_LVDS port map
(I=>clk_external, O=>clk_internal);
IBUFG_LVDS gclk0_p (.I(clk_external),
.O(clk_internal));
NET clk_external LOC = GCLKPAD3;
Virtex™-E 1.8 V Field Programmable Gate Arrays
P213 P215 P210 P209
P213 P215 P210 P209
D14
D17
A17
C11
E13
A20
C22
C15
E17
A6
B8
P
GCLK 3
C17
C18
C22
C17
A15
B11
B13
A22
A15
C6
A7
N
B14
A16
D17
A11
C13
D21
B22
E15
D17
C9
A7
P
GCLK 2
A13
B16
E17
D11
F14
A19
D22
E16
J18
B7
A8
N
AF14
AK16
AB13
AU22
AY22
AK16
AJ17
Al19
P89
P89
M7
R8
Yll
P
GCLK 1
AM18
AW21
AD14
AA11
AF13
AH16
AL17
AT22
AL17
P87
P87
M6
T8
N
AW19
AE13
AH18
AL16
AL17
AA14
BA22
Module 2 of 4
AJ16
W12
P92
P92
K7
N8
P
GCLK 0
AM17
AW20
AM18
AC13
AH15
AC14
AT21
AF16
U12
P93
P93
N8
N9
N
47