XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 56

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 43: Output Library Macros
Creating LVDS Output 3-State Buffers
LVDS output 3-state buffers can be placed in a wide number
of IOB locations. The exact locations are dependent on the
package used. The Virtex-E package information lists the
possible locations as IO_L#P for the P-side and IO_L#N for
the N-side, where # is the pair number.
HDL Instantiation
Both output 3-state buffers are required to be instantiated in
the design and placed on the correct IO_L#P and IO_L#N
locations. The IOB must have the same net source the fol-
lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state
clock enable (TCE), output (O), output clock enable (OCE).
In addition, the output (O) pins must be inverted with
respect to each other, and if output registers are used, the
INIT states must be opposite values (one High and one
Low). If 3-state registers are used, they must be initialized to
the same state. Failure to follow these rules leads to DRC
errors in the software.
Module 2 of 4
50
OBUFDS_FD_LVDS
OBUFDS_FDE_LVDS
OBUFDS_FDC_LVDS
OBUFDS_FDCE_LVDS
OBUFDS_FDP_LVDS
OBUFDS_FDPE_LVDS
OBUFDS_FDR_LVDS
OBUFDS_FDRE_LVDS
OBUFDS_FDS_LVDS
OBUFDS_FDSE_LVDS
OBUFDS_LD_LVDS
OBUFDS_LDE_LVDS
OBUFDS_LDC_LVDS
OBUFDS_LDCE_LVDS
OBUFDS_LDP_LVDS
OBUFDS_LDPE_LVDS
Name
D, GE, G, CLR
D, GE, G, PRE
D, CE, C, CLR
D, CE, C, PRE
D, CE, C, R
D, CE, C, S
DD, CE, C
D, C, PRE
D, G, CLR
D, G, PRE
D, C, CLR
D, GE, G
D, C, R
D, C, S
Inputs
D, C
D, G
Outputs
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
www.xilinx.com
VHDL Instantiation
Verilog Instantiation
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the .ucf or .ncf file.
Synchronous vs. Asynchronous 3-State Outputs
If the outputs are synchronous (registered in the IOB), then
any IO_L#P|N pair can be used. If the outputs are asynchro-
nous (no output register), then they must use one of the
pairs that are part of the same IOB group at the end of a
ROW or COLUMN in the device. This applies for either the
3-state pin or the data out pin.
LVDS pairs that can be used as asynchronous outputs are
listed in the Virtex-E pinout tables. Some pairs are marked
as “asynchronous capable” for all devices in that package,
and others are marked as available only for that device in
the package. If the device size might be changed at some
point in the product lifetime, then only the common pairs for
all packages should be used.
Adding Output and 3-State Registers
All LVDS buffers can have an output register in the IOB. The
output registers must be in both the P-side and N-side IOBs.
All the normal IOB register options are available (FD, FDE,
FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,
LDE, LDC, LDCE, LDP, LDPE). The register elements can
be inferred or explicitly instantiated in the HDL code.
Special care must be taken to insure that the D pins of the
registers are inverted and that the INIT states of the regis-
ters are opposite. The 3-state (T), 3-state clock enable
(CE), clock pin (C), output clock enable (CE) and set/reset
(CLR/PRE or S/R) pins must connect to the same source.
Failure to do this leads to a DRC error in the software.
data0_p:
(I=>data_int(0), T=>data_tri,
O=>data_p(0));
data0_inv: INV port map
(I=>data_int(0), O=>data_n_int(0));
data0_n:
(I=>data_n_int(0), T=>data_tri,
O=>data_n(0));
OBUFT_LVDS data0_p
.T(data_tri), .O(data_p[0]));
INV
.O(data_n_int[0]);
OBUFT_LVDS data0_n
.T(data_tri), .O(data_n[0]));
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
data0_inv (.I(data_int[0],
OBUFT_LVDS port map
OBUFT_LVDS port map
Production Product Specification
DS022-2 (v2.8) January 16, 2006
(.I(data_n_int[0]),
(.I(data_int[0]),
R