XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 57

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs.
To improve design coding times VHDL and Verilog synthe-
sis macro libraries have been developed to explicitly create
these structures. The input library macros are listed below.
The 3-state is configured to be 3-stated at GSR and when
the PRE,CLR,S or R is asserted and shares it's clock
enable with the output register. If this is not desirable then
the library can be updated by the user for the desired func-
tionality. The O and OB inputs to the macros are the exter-
nal net connections.
Creating a LVDS Bidirectional Buffer
LVDS bidirectional buffers can be placed in a wide number
of IOB locations. The exact locations are dependent on the
package used. The Virtex-E package information lists the
possible locations as IO_L#P for the P-side and IO_L#N for
the N-side, where # is the pair number.
HDL Instantiation
Both bidirectional buffers are required to be instantiated in
the design and placed on the correct IO_L#P and IO_L#N
locations. The IOB must have the same net source the fol-
lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state
clock enable (TCE), output (O), output clock enable (OCE).
In addition, the output (O) pins must be inverted with
respect to each other, and if output registers are used, the
INIT states must be opposite values (one HIGH and one
LOW). If 3-state registers are used, they must be initialized
to the same state. Failure to follow these rules leads to DRC
errors in the software.
VHDL Instantiation
Verilog Instantiation
DS022-2 (v2.8) January 16, 2006
Production Product Specification
data0_p:
(I=>data_out(0), T=>data_tri,
IO=>data_p(0), O=>data_int(0));
data0_inv: INV
(I=>data_out(0),
data0_n
(I=>data_n_out(0), T=>data_tri,
IO=>data_n(0), O=>open);
IOBUF_LVDS data0_p(.I(data_out[0]),
.T(data_tri), .IO(data_p[0]),
.O(data_int[0]);
INV
.O(data_n_out[0]);
IOBUF_LVDS
data0_n(.I(data_n_out[0]),.T(data_tri),.
IO(data_n[0]).O());
R
: IOBUF_LVDS port map
data0_inv (.I(data_out[0],
IOBUF_LVDS port map
O=>data_n_out(0));
port map
www.xilinx.com
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the .ucf or .ncf file.
Synchronous vs. Asynchronous Bidirectional
Buffers
If the output side of the bidirectional buffers are synchro-
nous (registered in the IOB), then any IO_L#P|N pair can be
used. If the output side of the bidirectional buffers are asyn-
chronous (no output register), then they must use one of the
pairs that is a part of the asynchronous LVDS IOB group.
This applies for either the 3-state pin or the data out pin.
The LVDS pairs that can be used as asynchronous bidirec-
tional buffers are listed in the Virtex-E pinout tables. Some
pairs are marked as asynchronous capable for all devices in
that package, and others are marked as available only for
that device in the package. If the device size might change
at some point in the product’s lifetime, then only the com-
mon pairs for all packages should be used.
Adding Output and 3-State Registers
All LVDS buffers can have an output and input registers in
the IOB. The output registers must be in both the P-side and
N-side IOBs, the input register is only in the P-side. All the
normal IOB register options are available (FD, FDE, FDC,
FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE,
LDC, LDCE, LDP, LDPE). The register elements can be
inferred or explicitly instantiated in the HDL code. Special
care must be taken to insure that the D pins of the registers
are inverted and that the INIT states of the registers are
opposite. The 3-state (T), 3-state clock enable (CE), clock
pin (C), output clock enable (CE), and set/reset (CLR/PRE
or S/R) pins must connect to the same source. Failure to do
this leads to a DRC error in the software.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs. To improve design coding times
VHDL and Verilog synthesis macro libraries have been
developed to explicitly create these structures. The bidirec-
tional I/O library macros are listed in
configured to be 3-stated at GSR and when the PRE,CLR,S
or R is asserted and shares its clock enable with the output
and input register. If this is not desirable then the library can
be updated be the user for the desired functionality. The I/O
and IOB inputs to the macros are the external net connec-
tions.
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table
44. The 3-state is
Module 2 of 4
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