EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 187
EZ80L92AZ050SG
Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG
EZ80L92AZ050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
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PS013014-0107
ZDI Bus Status Register
The ZDI Bus Status register monitors BUSACKs during DEBUG mode. See
Table 105. ZDI Bus Control Register (ZDI_BUS_STAT = 17h in the ZDI
Register Read-Only Address Space)
Bit
Position
[7:0]
ZDI_RD_L,
ZDI_RD_H,
or
ZDI_RD_U
Bit
Reset
CPU Access
Note: R = Read-only.
Bit
Position
7
ZDI_BUSAcK_En
6
ZDI_BUS_STAT
[5:0]
00h–FFh Values read from the memory location as requested by
000000 Reserved.
Value
Value
0
1
0
1
R
7
0
the ZDI Read Control register during a ZDI Read
operation. The 24-bit value is supplied by {ZDI_RD_U,
ZDI_RD_H, ZDI_RD_L}.
Description
Description
Bus requests by external peripherals using the
BUSREQ pin are ignored. The bus acknowledge signal,
BUSACK, is not asserted.
Bus requests by external peripherals using the
BUSREQ pin are accepted. A bus acknowledge occurs
at the end of the current ZDI operation. The bus
acknowledge is indicated by asserting the BUSACK pin.
Address and data buses are not relinquished to an
external peripheral. bus acknowledge is deasserted
(BUSACK pin is High).
Address and data buses are relinquished to an external
peripheral. bus acknowledge is asserted (BUSACK pin
is Low).
R
6
0
R
5
0
R
4
0
R
3
0
Product Specification
R
2
0
ZiLOG Debug Interface
eZ80L92 MCU
R
1
0
Table
105.
R
0
0
181
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