EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 90
EZ80L92AZ050SG
Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG
EZ80L92AZ050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
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- Download datasheet (3Mb)
PS013014-0107
Note:
Table 33. Timer Data Registers—Low Byte (TMR0_DR_L = 0081h,
TMR1_DR_L = 0084h, TMR2_DR_L = 0087h, TMR3_DR_L = 008Ah,
TMR4_DR_L = 008Dh, or TMR5_DR_L = 0090h)
Timer Data Registers—High Byte
This Read-Only register returns the High byte of the current count value of the selected
timer. The Timer Data Register—High Byte, detailed in
timer is in operation. Reading the current count value does not affect timer operation. To
read the 16-bit data of the current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]},
first read the Timer Data Register—Low Byte and then read the Timer Data Register—
High Byte. The Timer Data Register—High Byte value is latched when a Read of the
Timer Data Register—Low Byte occurs.
The timer data registers and timer reload registers share the same address space.
Table 34. Timer Data Registers—High Byte (TMR0_DR_H = 0082h,
TMR1_DR_H = 0085h, TMR2_DR_H = 0088h, TMR3_DR_H = 008Bh,
TMR4_DR_H = 008Eh, or TMR5_DR_H = 0091h)
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
TMRx_DR_L
Bit
Reset
CPU Access
Note: R = Read only.
00h–FFh These bits represent the Low byte of the 2-byte timer data
Value
R
R
7
0
7
0
Description
value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 7
of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16-bit
timer data value.
R
R
6
0
6
0
R
R
5
0
5
0
R
R
4
0
4
0
Table
R
R
3
0
3
0
34, can be read while the
Programmable Reload Timers
Product Specification
R
R
2
0
2
0
eZ80L92 MCU
R
R
1
0
1
0
R
R
0
0
0
0
84
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