CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet - Page 14

• Manufacturer Part Number: CS42528-DQZ
• Description: IC CODEC S/PDIF RCVR 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42528-DQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 114dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1503 - BOARD EVAL FOR CS42528/CS49300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

14
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI
(For CQZ, T
5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, C
Notes:
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
20. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
21. Data must be held for sufficient time to bridge the transition time of CCLK.
22. For f
A
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum
allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should
be safe for all possible conditions.
= -10 to +70° C; For DQZ, T
sck
<1 MHz.
Parameter
CDOUT
CDIN
CCLK
CS
t css
Figure 4. Control Port Timing - SPI Format
t r2
A
= -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to
t dsu
L
t scl
t f2
= 30 pF)
(Note 20)
(Note 21)
(Note 22)
(Note 22)
t sch
t dh
t pd
Symbol
f
t
t
t
t
t
t
t
csh
sch
dsu
t
t
t
t
sck
css
scl
dh
pd
r1
f1
r2
f2
Min
1.0
20
66
66
40
15
0
-
-
-
-
-
t csh
™
Typ
FORMAT
-
-
-
-
-
-
-
-
-
-
-
-
Max
100
100
6.0
50
25
25
-
-
-
-
-
-
CS42528
DS586F1
Units
MHz
µ s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns