CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet - Page 48
![IC CODEC S/PDIF RCVR 64-LQFP](/photos/6/80/68091/mfg_cs425_series_sml.jpg)
CS42528-DQZ
Manufacturer Part Number
CS42528-DQZ
Description
IC CODEC S/PDIF RCVR 64-LQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet
1.CS42528-CQZ.pdf
(91 pages)
Specifications of CS42528-DQZ
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 114
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
8
No. Of Input Channels
2
No. Of Output Channels
8
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
114dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1503 - BOARD EVAL FOR CS42528/CS49300
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS42528-DQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Company:
Part Number:
CS42528-DQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
48
6.4
6.4.1
6.4.2
6.4.3
6.4.4
CODEC_FM1 CODEC_FM0
7
Functional Mode (address 03h)
CODEC FUNCTIONAL MODE (CODEC_FMX)
SERIAL AUDIO INTERFACE FUNCTIONAL MODE (SAI_FMX)
ADC SERIAL PORT SELECT (ADC_SP SELX)
DAC DE-EMPHASIS CONTROL (DAC_DEM)
Selects the required range of sample rates for all converters clocked from the Codec serial port
(CODEC_SP). Bits must be set to the corresponding sample rate range when the CODEC_SP is in Master
or Slave Mode.
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 192 kHz sample rates)
11 - Reserved
Function:
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 192 kHz sample rates)
11 - Reserved
Function:
Default = 00
00 - Serial data on CX_SDOUT pin, clocked from the CODEC_SP. S/PDIF data on SAI_SDOUT pin.
01 - Serial data on CX_SDOUT pin, clocked from the SAI_SP. S/PDIF data on SAI_SDOUT pin.
10 - Serial data on SAI_SDOUT pin, clocked from the SAI_SP. No S/PDIF data available.
11 - Reserved
Function:
Default = 0
Function:
Selects the required range of sample rates for the Serial Audio Interface port (SAI_SP). These bits
must be set to the corresponding sample rate range when the SAI_SP is in Master or Slave Mode.
Selects the desired clocks and routing for the ADC serial output.
Enables the digital filter to maintain the standard 15µs/50µs digital de-emphasis filter response at the
auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless
of this register setting, at any other sample rate. If the FRC_PLL_LK bit is set to a ‘1’b, the auto-detect
sample rate feature is disabled. To apply the correct de-emphasis filter, use the DE-EMPH bits in the
6
SAI_FM1
5
SAI_FM0
4
ADC_SP SEL1 ADC_SP SEL0
3
2
DAC_DEM
1
CS42528
RCVR_DEM
DS586F1
0