CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet - Page 76

• Manufacturer Part Number: CS42528-DQZ
• Description: IC CODEC S/PDIF RCVR 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42528-DQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 114dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1503 - BOARD EVAL FOR CS42528/CS49300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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9.2.2
9.3
9.3.1
User (U) Data E Buffer Access
Entire blocks of U data are buffered using a cascade of two block-sized RAMs to perform the buffering as
described in the Channel Status section. The user has access to the E buffer through the control port Data
Buffer which is mapped into the register space of the CS42528. The Data Buffer must first be configured to
point to the address space of the U data. This is accomplished by setting the BSEL bit to ‘1’ in the register
“Channel Status Data Buffer Control (address 24h)” on page
The user can configure the Interrupt Mask Register to cause an interrupt whenever any data bit changes
are detected when D to E Channel Status buffer transfers occur. If no data bits have changed within the
current transfer of data from D to E, no interrupt will be generated. This allows determination of the accept-
able time periods to interact with the E buffer. See
tails.
The U buffer access only operates in Two-Byte Mode, since there is no concept of A and B blocks for user
data. The arrangement of the data is as follows: Bit15[A7]Bit14[B7]Bit13[A6]Bit12[B6]...Bit1[A0]Bit0[B0].
The arrangement of the data in each byte is as follows: MSB is the first received bit and is the first transmit-
ted bit. The first byte read is the first byte received, and the first byte sent is the first byte transmitted. When
two bytes are read from the E buffer, the bits are presented in the following arrangement:
A[7]B[7]A[6]B[6]....A[0]B[0].
9.3.1.1
The CS42528 can automatically detect various serial audio input formats. The Receiver Status register
(08h) is used to indicate a detected format. The register will indicate if uncompressed PCM data, IEC61937
data, DTS-LD data, DTS-CD data, HDCD data, or digital silence was detected. Additionally, the IEC61937
Pc/Pd burst preambles are available in registers 09h-0Ch. See the register descriptions for more informa-
tion.
Serial Copy Management System (SCMS)
The CS42528 allows read access to all the channel status bits. For consumer mode SCMS compliance,
the host microcontroller needs to read and interpret the Category Code, Copy bit and L bit appropriately.
Non-Audio Auto-Detection
The CS42528 S/PDIF receiver can detect non-audio data originating from AC-3 or MPEG encoders. This
is accomplished by looking for a 96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000,
0xF872, and 0x4E1F. When the sync code is detected, an internal AUTODETECT signal will be asserted.
If no additional sync codes are detected within the next 4096 frames, AUTODETECT will be de-asserted
until another sync code is detected. The AUDIO bit in the Receiver Channel Status register is the logical
OR of AUTODETECT and the received channel status bit 1. If non-audio data is detected, the data will
be processed exactly as if it were normal audio. It is up to the user to mute the outputs as required.
Format Detection
“Interrupt Mask (address 21h)” on page 64
65.
CS42528
for more de-
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