CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet - Page 36

• Manufacturer Part Number: CS42528-DQZ
• Description: IC CODEC S/PDIF RCVR 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42528-DQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 114dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1503 - BOARD EVAL FOR CS42528/CS49300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

36
Functional Mode Register (addr = 03h)
Interface Format Register (addr = 04h)
Misc. Control Register (addr = 05h)
ADC Mode
SAI_SDOUT=ADC Data
Set CODEC_FMx = 00,01,10
Set SAI_FMx = 00,01,10
Set ADC_SP SELx = 10
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01
Set DAC_OLx bits = 00,01,10
Set CODEC_SP M/S = 1
Set SAI_SP M/S = 0 or 1
Set EXT ADC SCLK = 0
CX_SDOUT= not used
4.6.4.4
This configuration will support up to 8 channels of DAC data 6 channels of ADC data and no channels of
S/PDIF received data. OLM Config #4 will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit
DAC samples at an Fs of 48 kHz. Since the ADC’s data stream is configured to use the SAI_SDOUT output
and the internal and external ADCs are clocked from the SAI_SP, the sample rate for the CODEC Serial
Port can be different from the sample rate of the Serial Audio Interface serial port.
Register / Bit Settings
Line Mode
One-Line
One-Line
Not One-
Mode #1
Mode #2
OLM Config #4
CS5361
CX_SCLK=64 Fs
CX_LRCK=SSM/DSM/QSM
SAI_SCLK=64 Fs
SAI_LRCK=SSM/DSM/QSM
CX_SCLK=64 Fs
CX_LRCK=SSM/DSM/QSM
SAI_SCLK=128 Fs
SAI_LRCK=SSM
CS5361
SDOUT1
SDOUT2
Not One Line Mode
SCLK
LRCK
MCLK
not valid
Figure 19. OLM Configuration #4
RMCK
ADCIN1
ADCIN2
CS42528
SAI_SDOUT
Configure ADC data to use SAI_SDOUT and SAI_SP Clocks. S/PDIF data
CX_SDOUT
SAI_LRCK
SAI_SCLK
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
CX_LRCK
CX_SCLK
CX_LRCK can run at SSM, DSM, or QSM independent of SAI_LRCK
SAI_LRCK can run at SSM, DSM, or QSM independent of CX_LRCK
CX_SCLK=128 Fs
CX_LRCK=SSM/DSM
SAI_SCLK=64 Fs
SAI_LRCK=SSM/DSM/QSM
CX_SCLK=128 Fs
CX_LRCK=SSM/DSM
SAI_SCLK=128 Fs
SAI_LRCK=SSM
Select ADC operating mode, see table below for valid combinations
Select DAC operating mode, see table below for valid combinations
Select the digital interface format when not in one line mode
One Line Mode #1
Identify external ADC clock source as SAI Serial Port.
Set ADC Serial Port to master mode or slave mode.
64Fs,128Fs,256Fs
ADC Data
64Fs,128Fs
DAC Mode
not valid
Set DAC Serial Port to master mode.
is not supported in this configuration
SDIN_PORT1
LRCK_PORT2
SDIN_PORT2
SCLK_PORT1
LRCK_PORT1
SCLK_PORT2
LRCK_PORT3
SDOUT1_PORT3
SDOUT2_PORT3
SDOUT3_PORT3
SDOUT4_PORT3
MCLK
SCLK_PORT3
DIGITAL AUDIO
PROCESSOR
Description
CX_SCLK=256 Fs
CX_LRCK=SSM
SAI_SCLK=64 Fs
SAI_LRCK=SSM/DSM/QSM
CX_SCLK=256 Fs
CX_LRCK=SSM
SAI_SCLK=128 Fs
SAI_LRCK=SSM
One Line Mode #2
not valid
CS42528
DS586F1