CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet - Page 63

IC CODEC S/PDIF RCVR 64-LQFP

CS42528-DQZ

Manufacturer Part Number
CS42528-DQZ
Description
IC CODEC S/PDIF RCVR 64-LQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet

Specifications of CS42528-DQZ

Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 114
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
8
No. Of Input Channels
2
No. Of Output Channels
8
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
114dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1503 - BOARD EVAL FOR CS42528/CS49300
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS42528-DQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS42528-DQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
DS586F1
6.19
6.19.1 TXP MULTIPLEXER (TMUXX)
6.19.2 RECEIVER MULTIPLEXER (RMUXX)
6.20
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the reg-
ister was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the
register. Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will
always be “0” in this register.
Reserved
UNLOCK
7
7
Receiver Mode Control 2 (address 1Fh)
Interrupt Status (address 20h) (Read Only)
Default = 000
Function:
Selects which of the eight receiver inputs will be mapped directly to the TXP output pin.
Default = 000
Function:
Selects which of the eight receiver inputs will be mapped to the internal receiver.
Reserved
TMUX2
6
6
RMUX2
TMUX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TMUX1
QCH
5
5
RMUX1
TMUX1
Table 19. Receiver Input Selection
Table 18. TXP Output Selection
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TMUX0
DETC
4
4
RMUX0
TMUX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
DETU
3
3
Output from pin RXP0
Output from pin RXP1
Output from pin RXP2
Output from pin RXP3
Output from pin RXP4
Output from pin RXP5
Output from pin RXP6
Output from pin RXP7
Input from pin RXP0
Input from pin RXP1
Input from pin RXP2
Input from pin RXP3
Input from pin RXP4
Input from pin RXP5
Input from pin RXP6
Input from pin RXP7
Description
Description
Reserved
RMUX2
2
2
OverFlow
RMUX1
1
1
CS42528
RMUX0
RERR
0
0
63

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