CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet - Page 25

• Manufacturer Part Number: CS42528-DQZ
• Description: IC CODEC S/PDIF RCVR 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42528-DQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 114dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1503 - BOARD EVAL FOR CS42528/CS49300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DS586F1
4.5
4.5.1
Clock Generation
The clock generation for the CS42528 is shown in the figure below. The internal MCLK is derived from the
output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the
SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL
lock to the other source input.
(slave mode)
S/PDIF Clock
SAI_LRCK
OMCK
Recovered
PLL and Jitter Attenuation
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming S/PDIF data stream.
There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is im-
portant. For this reason, the PLL has been designed to have good jitter attenuation characteristics as
shown in Figure 28 on page 79.
The PLL can be configured to lock onto the incoming SAI_LRCK signal from the Serial Audio Interface
Port and generate the required internal master clock frequency. By setting the PLL_LRCK bit to a ‘1’ in
the register
generate an output master clock (RMCK) of 256Fs.
Fs values for SAI_LRCK.
See
components, optimal layout guidelines, and jitter-attenuation characteristics.
“Appendix C: PLL Filter” on page 77
0
1
“Clock Control (address 06h)” on page
PLL_LRCK bit
PLL (256Fs)
49.152 MHz
8.192 -
Figure 9. CS42528 Clock Generation
Internal
00
01
MCLK
(manual or auto
SW_CTRLx bits
switch)
Auto Detect
Input Clock
X2
1,1.5, 2, 4
for more information concerning PLL operation, required filter
2
4
00
01
10
11
Table 2
53, the PLL will lock to the incoming SAI_LRCK and
RMCK_DIVx bits
double
double
speed
speed
speed
speed
speed
speed
single
single
quad
quad
256
128
64
4
2
1
shows the output of the PLL with typical input
SAI_FMx bits
CODEC_FMx bits
00
01
10
00
01
10
00
01
10
00
01
10
128FS
256FS
128FS
256FS
ADC_SP SELx bits
or ADC_OLx bits
not OLM
not OLM
OLM #1
OLM #1
OLM #2
OLM #2
ADC_OLx and
DAC_OLx
RMCK
CX_LRCK
CX_SCLK
SAI_LRCK
SAI_SCLK
CS42528
25