CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet - Page 34

• Manufacturer Part Number: CS42528-DQZ
• Description: IC CODEC S/PDIF RCVR 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42528-DQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 114dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1503 - BOARD EVAL FOR CS42528/CS49300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

34
Functional Mode Register (addr = 03h)
Interface Format Register (addr = 04h)
Misc. Control Register (addr = 05h)
Set CODEC_FMx = SAI_FMx = 00,01,10
Set ADC_SP SELx = 10
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01,10
Set DAC_OLx bits = 00,01
Set CODEC_SP M/S = 1
Set SAI_SP M/S = 1
Set EXT ADC SCLK = 1
ADC Mode
SAI_SDOUT=ADC Data
CX_SDOUT= not used
4.6.4.2
This configuration will support up to 8 channels of DAC data or 6 channels of ADC data and no channels
of S/PDIF received data and will handle up to 20-bit samples at a sampling-frequency of 96 kHz on all chan-
nels for both the DAC and ADC. The output data stream of the internal and external ADCs is configured to
use the SAI_SDOUT output and run at the SAI_SP clock speeds.
Register / Bit Settings
Line Mode
Not One-
One-Line
One-Line
Mode #1
Mode #2
OLM Config #2
CX_SCLK=64 Fs
CX_LRCK=SSM/DSM/QSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
CX_SCLK=64 Fs
CX_LRCK=SSM/DSM
SAI_SCLK=128 Fs
SAI_LRCK=CX_LRCK
CX_SCLK=64 Fs
CX_LRCK=SSM
SAI_SCLK=256 Fs
SAI_LRCK=CX_LRCK
CS5361
CS5361
SDOUT1
SDOUT2
Not One-Line Mode
SCLK
MCLK
LRCK
Figure 17. OLM Configuration #2
RMCK
ADCIN1
ADCIN2
CS42528
Configure ADC data to use SAI_SDOUT and SAI_SP Clocks. S/PDIF data
CX_LRCK must equal SAI_LRCK; sample rate conversion not supported
SAI_SDOUT
CX_SDOUT
SAI_SCLK
SAI_LRCK
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
CX_LRCK
CX_SCLK
Select ADC operating mode, see table below for valid combinations
Select DAC operating mode, see table below for valid combinations
CX_SCLK=128 Fs
CX_LRCK=SSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
CX_SCLK=128 Fs
CX_LRCK=SSM
SAI_SCLK=128 Fs
SAI_LRCK=CX_LRCK
Select the digital interface format when not in one line mode
Identify external ADC clock source as CODEC Serial Port.
One-Line Mode #1
Set Serial Audio Interface Port to master mode.
64Fs,128Fs
64Fs,128Fs,
ADC Data
Set CODEC Serial Port to master mode.
not valid
256Fs
DAC Mode
is not supported in this configuration
SDIN_PORT1
SDIN_PORT2
MCLK
SCLK_PORT1
LRCK_PORT1
SCLK_PORT2
SCLK_PORT3
LRCK_PORT3
SDOUT1_PORT3
SDOUT2_PORT3
SDOUT3_PORT3
SDOUT4_PORT3
LRCK_PORT2
DIGITAL AUDIO
PROCESSOR
Description
One-Line Mode #2
not valid
not valid
not valid
CS42528
DS586F1