CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet - Page 32
![IC CODEC S/PDIF RCVR 64-LQFP](/photos/6/80/68091/mfg_cs425_series_sml.jpg)
CS42528-DQZ
Manufacturer Part Number
CS42528-DQZ
Description
IC CODEC S/PDIF RCVR 64-LQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet
1.CS42528-CQZ.pdf
(91 pages)
Specifications of CS42528-DQZ
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 114
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
8
No. Of Input Channels
2
No. Of Output Channels
8
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
114dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1503 - BOARD EVAL FOR CS42528/CS49300
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS42528-DQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Company:
Part Number:
CS42528-DQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
32
4.6.3
SAI_SCLK
SAI_LRCK
CX_SCLK
ADCIN1/2
CX_LRCK
ADCIN1/ADCIN2 Serial Data Format
The two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, support
only left-justified, 24-bit samples at 64Fs or 128Fs. This interface is not affected by any of the serial port
configuration register bit settings. These serial data lines are used when supporting One-Line Mode of
operation with external ADCs attached. If these signals are not being used, they should be tied together
and wired to GND via a pull-down resistor.
For proper operation, the CS42528 must be configured to select which SCLK/LRCK is being used to clock
the external ADCs. The EXT ADC SCLK bit in register
set accordingly. Set this bit to ‘1’ if the external ADCs are wired using the CODEC_SP clocks. If the ADCs
are wired to use the SAI_SP clocks, set this bit to ‘0’.
Left-Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
MSB
24
-1 -2 -3 -4 -5
Figure 15. ADCIN1/ADCIN2 Serial Audio Format
64, 128 Fs
64 Fs
not supported
+5 +4
Left Channel
SCLK Rate(s)
+3 +2 +1
LSB
Single-Speed Mode, Fs= 32, 44.1, 48 kHz
Double-Speed Mode, Fs= 64, 88.2, 96 kHz
Quad-Speed Mode, Fs= 176.4, 192 kHz
“Misc Control (address 05h)” on page 51
MSB
-1 -2 -3 -4
Notes
+5 +4
Right Channel
+3 +2 +1
LSB
CS42528
DS586F1
must be