CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet - Page 24

• Manufacturer Part Number: CS42528-DQZ
• Description: IC CODEC S/PDIF RCVR 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42528-DQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 114dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1503 - BOARD EVAL FOR CS42528/CS49300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

24
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
S/PDIF Receiver
The CS42528 includes an S/PDIF digital audio receiver. The S/PDIF receiver accepts and decodes digital
audio data according to the IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The receiver con-
sists of an 8:2 multiplexer input stage driven through pins RXP0 and RXP1/GPO1 - RXP7/GPO7, a PLL
based clock recovery circuit, and a decoder which separates the audio data from the channel status and
user data. A comprehensive buffering scheme provides read access to the channel status and user data.
External components are used to terminate and isolate the incoming data cables from the CS42528. These
components and required circuitry are detailed in the CDB42528.
8:2 S/PDIF Input Multiplexer
The CS42528 contains an 8:2 S/PDIF Input Multiplexer to accommodate up to eight channels of input dig-
ital audio data. Digital audio data is single-ended and input through the RXP0 and
RXP1/GPO1-RXP7/GPO7 pins. Any one of these inputs can be multiplexed to the input of the S/PDIF
receiver and to the S/PDIF output pin TXP.
When any portion of the multiplexer is implemented, unused RXP0 and RXPx/GPOx pins should be tied
to a 0.01uF capacitor to ground. The receiver multiplexer select line control is accessed through bits
RMUX2:0 in the Receiver Mode Control 2 register on
accessed through bits TMUX2:0 in the same register. The multiplexer defaults to RXP0 for both functions.
Error Reporting and Hold Function
While decoding the incoming S/PDIF data stream, the CS42528 can identify several kinds of error, indi-
cated in the register
Hold Function” on page 74
Channel Status Data Handling
The first 2 bytes of the Channel Status block (C data) are decoded into the Receiver Channel Status reg-
ister (See
Handling” on page 74
User Data Handling
The incoming User (U) data is buffered in a user accessible buffer. If the U data bits have been encoded
as Q-channel subcode, the data is decoded and presented in 10 consecutive register locations, address
30h to 39h. The user can configure the Interrupt Mask Register to cause interrupts to indicate the decod-
ing of a new Q-channel block, which may be read through the control port. See
Access” on page 76
Non-Audio Auto-Detection
A S/PDIF data stream may be used to convey non-audio data, thus it is important to know whether the
incoming data stream is digital PCM audio samples or not. This information is typically conveyed in chan-
nel status bit 1 (AUDIO), which is extracted automatically by the CS42528. Certain non-audio sources,
however, such as AC-3
properly set. See
face format detection.
“Receiver Channel Status (address 25h) (Read Only)” on page
“Non-Audio Auto-Detection” on page 76
“Receiver Errors (address 26h) (Read Only)” on page
for more information.
for more information.
®
or MPEG encoders, may not adhere to this convention, and the bit may not be
for more information.
page
for more information including details for inter-
63. The TXP multiplexer select line control is
66). See
67. See
“User (U) Data E Buffer
“Channel Status Data
“Error Reporting and
CS42528
DS586F1