CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet - Page 35

• Manufacturer Part Number: CS42528-DQZ
• Description: IC CODEC S/PDIF RCVR 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42528-DQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 114dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1503 - BOARD EVAL FOR CS42528/CS49300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DS586F1
This One Line Mode configuration #3 will support up to 8 channels of DAC data, 6 channels of ADC data and 2
channels of S/PDIF received data and will handle up to 20-bit samples at a sampling frequency of 48 kHz on all
channels for both the DAC and ADC. The output data stream of the internal and external ADCs is configured to use
the CX_SDOUT output and run at the CODEC_SP clock speeds. One Line Mode #2, which supports 24-bit sam-
ples, is not supported by this configuration.
Functional Mode Register (addr = 03h)
Interface Format Register (addr = 04h)
Misc. Control Register (addr = 05h)
SAI_SDOUT=S/PDIF Data
Set CODEC_FMx = SAI_FMx = 00,01,10
Set ADC_SP SELx = 00
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01
Set DAC_OLx bits = 00,01
Set CODEC_SP M/S = 1
Set SAI_SP M/S = 0 or 1
Set EXT ADC SCLK = 1
ADC Mode
CX_SDOUT= ADC Data
4.6.4.3
Register / Bit Settings
Line Mode
One-Line
One-Line
Not-One
Mode #1
Mode #2
OLM Config #3
CS5361
CS5361
CX_SCLK=64 Fs
CX_LRCK=SSM/DSM/QSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
CX_SCLK=128 Fs
CX_LRCK=SSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
SDOUT1
SDOUT2
SCLK
MCLK
LRCK
Not One-Line Mode
not valid
Figure 18. OLM Configuration #3
RMCK
ADCIN1
ADCIN2
CS42528
SAI_SDOUT
CX_SDOUT
Configure ADC data to use CX_SDOUT and CODEC_SP Clocks. S/PDIF
CX_LRCK must equal SAI_LRCK; sample rate conversion not supported
SAI_SCLK
SAI_LRCK
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
CX_SCLK
CX_LRCK
Select ADC operating mode, see table below for valid combinations
Select DAC operating mode, see table below for valid combinations
CX_SCLK=128 Fs
CX_LRCK=SSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
CX_SCLK=128 Fs
CX_LRCK=SSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
Set Serial Audio Interface Port to master mode or slave mode.
Select the digital interface format when not in one line mode
Identify external ADC clock source as CODEC Serial Port.
One-Line Mode #1
64Fs,128Fs
ADC Data
SPDIF Data
64Fs
Set CODEC Serial Port to master mode.
not valid
DAC Mode
data is supported on SAI_SDOUT
SDIN_PORT1
SDIN_PORT2
MCLK
SCLK_PORT1
LRCK_PORT1
SCLK_PORT2
LRCK_PORT2
SCLK_PORT3
LRCK_PORT3
SDOUT1_PORT3
SDOUT2_PORT3
SDOUT3_PORT3
SDOUT4_PORT3
DIGITAL AUDIO
PROCESSOR
Description
One-Line Mode #2
not valid
not valid
not valid
CS42528
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