CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet - Page 55

• Manufacturer Part Number: CS42528-DQZ
• Description: IC CODEC S/PDIF RCVR 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42528-DQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 114dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1503 - BOARD EVAL FOR CS42528/CS49300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DS586F1
6.9.2
6.9.3
6.9.4
AES FORMAT DETECTION (AES FORMATX)
SYSTEM CLOCK SELECTION (ACTIVE_CLK)
RECEIVER CLOCK FREQUENCY (RCVR_CLKX)
Note:
Default = xxx
Function:
Default = x
0 - Output of PLL
1 - OMCK
Function:
Default = xxx
Function:
Format2
The CS42528 will auto-detect the AES format of the incoming S/PDIF stream and display the infor-
mation according to the following table.
This bit identifies the source of the internal system clock (MCLK).
The CS42528 detects the ratio between the OMCK and the recovered clock from the PLL. Given the
absolute frequency of OMCK, this ratio may be used to determine the absolute frequency of the PLL
clock.
If a 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz clock is applied to OMCK and the OMCK_FREQX
bits are set accordingly (see
of the PLL clock is reflected in the RCVR_CLKX bits according to
of the PLL clock does not match one of the frequencies given in
closest available value.
If the frequency of OMCK is not equal to 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz, the contents
of the RCVR_CLKX bits will be inaccurate and should be disregarded. In this case, an external con-
troller may use the contents of the OMCK/PLL_CLK ratio register and the known OMCK frequency to
determine the absolute frequency of the PLL clock.
AES
0
0
0
0
1
1
1
1
These bits are set to ‘111’b when the FRC_PLL_LK bit is ‘1’b.
Format1
AES
0
0
1
1
0
0
1
1
Format0
Table 13. AES Format Detection
AES
“OMCK Frequency (OMCK Freqx)” on page
0
1
0
1
0
1
0
1
Linear PCM
DTS
DTS
HDCD
IEC 61937
Reserved
Reserved
Reserved
®
®
-CD
-LD
®
Description
Table
Table
14, these bits will reflect the
14. If the absolute frequency
53), the absolute frequency
CS42528
55