CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet - Page 77
![IC CODEC S/PDIF RCVR 64-LQFP](/photos/6/80/68091/mfg_cs425_series_sml.jpg)
CS42528-DQZ
Manufacturer Part Number
CS42528-DQZ
Description
IC CODEC S/PDIF RCVR 64-LQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet
1.CS42528-CQZ.pdf
(91 pages)
Specifications of CS42528-DQZ
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 114
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
8
No. Of Input Channels
2
No. Of Output Channels
8
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
114dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1503 - BOARD EVAL FOR CS42528/CS49300
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS42528-DQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Company:
Part Number:
CS42528-DQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
DS586F1
10.APPENDIX C: PLL FILTER
The PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update information to
the PLL. This results in the PLL being immune to data-dependent jitter effects because the S/PDIF preambles do
not vary with the data.
The PLL has the ability to lock onto a wide range of input sample rates with no external component changes. The
nominal center sample rate is the sample rate that the PLL first locks onto upon application of an S/PDIF data
stream.
10.1 External Filter Components
10.1.1 General
Configuration 1
Configuration 2
Configuration 3
The PLL behavior is affected by the external filter component values and the locking mode as configured
by the LOCKM[1:0] bits in register 24h.
values and their associated locking modes.
INPUT
RFILT (kΩ) CFILT (µF) CRIP (pF) LOCKM[1:0]
2.55
2.55
1.37
and Charge Pump
Table 21. External PLL Component Values & Locking Modes
Comparator
Phase
÷
0.047
0.047
0.022
N
Figure 27. PLL Block Diagram
2200
2200
1000
Table 21
CFILT
RFILT
shows the supported configurations of PLL component
00
01
10
CRIP
Used for backward compatibility with Revision C
increased wideband jitter. Use this configuration
Provides improved in-band jitter rejection, with
Provides improved wideband jitter rejection in
Default configuration for Revision D devices.
for best DAC and ADC performance when
clocked from the PLL recovered clock.
Double- and Quad-Speed modes.
VCO
devices.
Notes
RM CK
CS42528
77