XCCACE-TQG144I Xilinx Inc, XCCACE-TQG144I Datasheet - Page 11

• Manufacturer Part Number: XCCACE-TQG144I
• Description: IC ACE CONTROLLER CHIP TQ144
• Manufacturer: Xilinx Inc

Specifications of XCCACE-TQG144I

• Controller Type: ACE Controller
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 30mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Other names: 122-1511-5

Controlling the Number of Reserved Sectors
Windows 2000, Windows NT, and Windows 98 default to
one reserved sector when formatting. Therefore, formatting
the CF card using these Windows operating systems is not
problematical in this regard.
In Windows XP, however, the DOS format command auto-
matically formats the CF card with from two to eight
reserved sectors, depending on the density of the CF card.
Microprocessor Interface (MPU)
The MPU Interface provides a useful means of monitoring
the status of and controlling the System ACE CF controller,
as well as CompactFlash card READ / WRITE data. The
MPU is not required for normal operation, but when used, it
provides numerous capabilities. This interface enables
communication between an MPU device and a Compact-
Flash module and the FPGA target system.
The MPU interface is composed of a set of registers that
provide a means for communicating with CompactFlash
control logic, configuration control logic, and other
resources in the System ACE CF controller. Specifically, this
interface can be used to read the identity of a Compact-
Flash device and read/write sectors from or to a Compact-
Flash device.
The MPU interface can also be used to control configuration
flow. The MPU interface enables monitoring of System ACE
CF controller configuration status and error conditions. The
MPU interface can be used to delay configuration, start con-
figuration, determine the source of configuration (Compact-
Flash or MPU), control the bitstream version, reset the
device, etc.
Two important issues should be understood when using the
microprocessor port:
•
•
Table 6: MPU Interface Port Signal Description
DS080 (v2.0) October 1, 2008
Product Specification
MPCE
Name
MPD
MPA
For the System ACE CF controller to be properly
synchronized, the device driving the MPU interface
must be synchronized to the CLK signal
The MPU must comply with System ACE timing
requirements
R
Width
16
7
1
Direction
In/Out
In
In
Active
LOW
N/A
N/A
Synchronous address inputs. The internal address register is loaded by MPA
by a combination of the rising edge of CLK and MPCE LOW.
Synchronous data input/output pins. Both the data input and output path are
registered and triggered by the rising edge of CLK.
Synchronous active LOW chip enable. MPCE LOW is used to enable the
MPU interface. MPCE LOW is also used in conjunction with MPOE LOW to
enable the MPD output.
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Because the DOS format command does not allow specifi-
cation of the number of reserved sectors, an alternate disk
formatting utility (such as mkdosfs, available from
http://www1.mager.org/mkdosfs) must be used. When
the CF card is correctly formatted, Windows XP can be
used to perform normal file access (read/write) operations
without causing any additional problems.
This general-purpose microprocessor interface can update
the CompactFlash, read the ACE status, or obtain direct
access to the JTAG configuration ports using the ACE
Microprocessor commands. This interface supports either
8-bit (default) or 16-bit data transfers. The bus width can be
configured dynamically.
All communications between the System ACE CF controller
and a host microprocessor involve transfer of data to or from
ACE registers. There are 128 addressable registers in 8-bit
mode and 64 addressable registers in 16-bit mode. For
easy selection of a new configuration from CompactFlash
data, the MPU interface allows for easy reconfiguration of
an FPGA chain or capability.
When using the MPU interface as the configuration source,
the CFGTCK output for the System ACE CF controller
device is derived from the CLK input to the System ACE CF
controller (supplied by the MPU), and the operating fre-
quency of the CFGTCK is the same as CLK.
•
•
The following sections describe supported operations when
using the MPU interface.
MPU Port Signal Description
MPU interface port signals are described in
The minimum clock operating frequency is 0 MHz.
The maximum clock operating frequency is either 33
MHz or the maximum JTAG TCK clock speed dictated
by the devices in the JTAG chain and/or the board
design. The lowest of these values should be used.
Description
System ACE CompactFlash Solution
Table
6.
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