XCCACE-TQG144I Xilinx Inc, XCCACE-TQG144I Datasheet - Page 34

• Manufacturer Part Number: XCCACE-TQG144I
• Description: IC ACE CONTROLLER CHIP TQ144
• Manufacturer: Xilinx Inc

Specifications of XCCACE-TQG144I

• Controller Type: ACE Controller
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 30mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Other names: 122-1511-5

System ACE CompactFlash Solution
DATABUFREG Register (BYTE address 40h-5Fh, WORD address 20h-2Fh)
The DATABUFREG register is the portal register to the data buffer that is used to transfer data between the MPU interface
and the CompactFlash and/or Configuration controllers. The description of the DATABUFREG register bits are shown in
Table
Table 19: DATABUFREG Register Bit Descriptions
Test JTAG Interface (TSTJTAG)
The Test JTAG Interface (TSTJTAG) supports IEEE 1149.1
Boundary-Scan operations on the System ACE CF control-
ler and all chained FPGA devices connected to the Config-
uration JTAG (CFGJTAG) port. This interface can also be
used to program the target FPGA chain on the CFGJTAG
port, using Xilinx or third-party JTAG programming tools.
The System ACE CF controller is fully compliant with the
IEEE 1149.1 Boundary-Scan standard, commonly referred
to as JTAG. As shown in
Port (TAP), instruction decoder, and the required IEEE
1149.1 Registers are included in the System ACE CF con-
troller to support the mandatory Boundary-Scan instruc-
tions. In addition, the Controller also supports an optional
32-bit identification register. Refer to the IEEE 1149.1
Boundary-Scan standard specification for a complete
description of the required instructions and detailed infor-
mation on JTAG.
34
Bit
10
11
12
13
14
15
9
0
1
2
3
4
5
6
7
8
19.
DATA00
DATA01
DATA02
DATA03
DATA04
DATA05
DATA06
DATA07
DATA08
DATA09
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
Name
Figure 16, page
Data buffer portal register:
• Data register bits are read-only when the DATABUFMODE bit in the STATUSREG
• DATABUFREG(07:00) are accessible in BYTE and WORD bus modes.
Data register:
• Data register bits are read-only when the DATABUFMODE bit in the STATUSREG
• DATABUFREG(15:08) are accessible in BYTE and WORD bus modes.
• During BYTE bus write mode, if the data buffer is ready, any writes to the
• During BYTE bus read mode, if the data buffer is ready, the DATABUFREG(15:00)
register is a 0, otherwise they are write-only when the DATABUFMODE bit is a 1.
register is a 0, otherwise they are write-only when the DATABUFMODE bit is a 1.
DATABUFREG(15:08) bits cause the DATABUFREG(15:00) contents to be written to
the data buffer.
register will hold the current value until the DATABUFREG(15:08) bits are read. After
DATABUFREG(15:08) is read, the DATABUFREG(15:00) register is loaded with any
pending new data.
35, a Test Access
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Table 20: System ACE CF Controller TAP Pins
When using the TSTJTAG interface as the configuration
source, the CFGTCK output of the System ACE CF
controller device is derived from the TSTTCK input. The
operating frequency of the CFGTCK is the same as
TSTTCK.
•
•
TSTTDI (TDI)
TSTTDO (TDO)
TSTTMS (TMS)
TSTTCK (TCK)
The minimum clock operating frequency is 0 MHz.
The maximum clock operating frequency is either
16.7 MHz or the maximum JTAG TCK clock speed
dictated by the devices in the JTAG chain and/or the
board design. The lowest of these values should be
used.
Description
Pins
Test Data In
Test Data Out
Test Mode Select
Test Clock
DS080 (v2.0) October 1, 2008
Description
Product Specification
R