TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 123
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TSI148-133CL
Manufacturer Part Number
TSI148-133CL
Description
IC PCI-VME BRIDGE 456PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
Tsi148&Trade;r
Datasheets
1.TSI148-133CL.pdf
(391 pages)
2.TSI148-133CL.pdf
(2 pages)
3.TSI148-133CL.pdf
(12 pages)
Specifications of TSI148-133CL
Applications
PCI-to-VME Bridge
Interface
PCI
Voltage - Supply
3.3V
Package / Case
456-PBGA
Mounting Type
Surface Mount
Package Type
BGA
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1906
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TSI148-133CL
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
TSI148-133CLY
Manufacturer:
TUNDRA
Quantity:
355
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5.3
Table 5: PCI Bus Configuration
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
FRAME__
1
1
1
1
1
Clocks
Tsi148 clocks are derived from the PCI/X bus clock. The PCI/X bus clock frequency can be
33, 66, 100, or 133 MHz.
The PCI/X clock frequency and bus mode is configured on the rising edge of LRSTI_ (see
Table
The PCI bus configuration signals are latched on the negation of LRSTI_. The Tsi148 expects
the PCI bus configuration signals to be valid from the time the PLL reset input is negated
(PLL_RSTI_) and remain valid until the LRSTI_ signal is negated. This allows the internal
PLL to lock to the PCI/X bus clock.
The configuration signals are only latched on the first rising edge of LRSTI_. If LRSTI_ is
asserted at a later time, the configuration signals are not latched again. However, if both
PURSTI_ and LRSTI_ are reasserted, then the configuration signal latches are opened and the
configuration signals are latched on the rising edge of LRSTI_.
The configuration signals are only latched once to make sure the PLL clock remains stable
through a PCI/X bus reset. This stability enables a subset of the VMEbus logic to function
while the PCI/X bus is in reset, including: the VMEbus SYSCLK, VMEbus arbiter, VMEbus
daisy chain signals, VMEbus General Control and Status register access, and VMEbus
Control and Control and Status register accesses.
IRDY_
1
1
1
1
1
5)
PCLK operation below 33 MHz is not recommended.
DEVSEL_
PCI Bus Signal
1
1
1
1
1
STOP_
1
1
1
0
0
TRDY_
1
1
0
1
0
5. Resets, Clocks, and Power-up Options > Clocks
M66EN
X
X
X
0
1
PCI-X
PCI-X
PCI-X
Mode
PCI
Bus
PCI
PCI
Min
33.3
66.6
100
50
50
PCI Clock
Frequency
(MHz)
133.3
Max
33.3
66.6
66.6
100
123
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