TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 82

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

3. PCI/X Interface > PCI-X Mode
3.3
3.3.1
3.3.1.1
82
PCI-X Mode
Tsi148 is compliant with the PCI-X Addendum to PCI Local Bus Specification
(Revision 1.0b).
PCI-X Target
The PCI-X Target supports 32-bit and 64-bit data transfers and 32-bit and 64-bit addresses.
The PCI-X Target supports configuration cycles to PCI-X configuration registers and memory
space accesses. The Linkage Module provides access to the combined register group and the
VMEbus. The VME Master provides the interface between the Linkage Module and the
VMEbus.
The PCI-X Target does not respond to PCI-X I/O transfers.
PCI-X Target Buffers
The PCI-X Target shares buffers between the PCI and PCI-X protocols. When the PCI-X bus
is configured for PCI-X mode, the entire 4 Kbyte PCI-X Target read buffer can be used. The
read buffer is segmented into two parts: a data queue and a command queue. The command
queue stores address and attributes from the PCI-X bus and can accept up to six split
transactions. The data queue stores up to 4 Kbyte of data.
The PCI-X Target read buffer stores the address and attributes of the transaction in the
command queue when servicing a read request from the PCI-X bus master. The requested
data comes from the VMEbus, through Linkage Module, to the PCI-X Target read buffer data
queue. The amount of data in read buffer depends on the requested byte-count in the attribute
phase of the PCI-X transaction.
The write buffer receives data and commands from the PCI-X bus. The write buffer
segmented into two parts: data queue and command queue. The 4 Kbyte data queue is
designed for large, burst transfers. The command queue stores address and attributes from
PCI-X transactions and can accept up to 40 entries. The write buffer is full when either the
command or data queue is full.
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13