TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 65

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

2.3.7
2.3.7.1
2.3.7.2
2.3.7.3
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
Tsi148 as a VMEbus System Controller
The Tsi148 supports the following system controller functions:
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Arbiter
The Tsi148 VMEbus arbiter is programmable. All three of the following arbitration modes
defined by the VMEbus standard are supported:
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A 16 us arbitration timer is included in the Tsi148 to prevent a bus lock-up from occurring
when no requester assumes mastership of the bus after the arbiter has issued a grant. This
timer can be enabled or disabled in the VMEbus Control and Status Register (see
Section 10.4.34 on page
IACK Daisy-Chain Driver
An IACK Daisy-Chain driver is included in the Tsi148 as part of the system controller
functionality. This feature ensures that the timing requirements for starting the IACK
Daisy-Chain are satisfied.
SYSRESET Driver
A SYSRESET driver is included in the Tsi148 to provide a global system reset. The SRSTO
signal is asserted in the following cases: the LSRSTI_ pin is asserted, the SRESET bit is
asserted in the VMEbus Control Status Register, or the PURSTI_ pin is asserted. The SRSTO
signal is always asserted for at least 200 ms. SRSTO is normally connected to the VMEbus
SYSRESET_ signal through an inverting open collector buffer.
VMEbus Arbiter with three modes of programmable arbitration:
— Priority (PRI)
— Round-Robin-Select (RRS)
— Single Level (SGL)
IACK Daisy-Chain Driver
SYSRESET Driver: Provides a global system reset
Global VMEbus Timer: Monitors the VMEbus and generates a BERR_ when there is no
VMEbus activity for the programmed value
System Clock Driver: Generates a 16 MHz system clock
Priority (PRI)
Round-Robin-Select (RRS)
Single Level (SGL)
253).
2. VME Interface > VME Master
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